Logical Implementation covers the RTL-to-Netlist stages of an ASIC development flow. This used to involve mainly synthesis to meet timing and area targets, plus some scan-insertion for DFT, but now covers a wider range of activities that can be critical to the optimisation and performance of your ASIC, including:
- RTL and DFT optimisation for performance, power, and area
- Synthesis trials to help select the ideal silicon process and IP for your application
- Insertion of Test and BIST structures into the RTL
- Synthesis of power management and power optimisation logic, using UPF/CPF
- Technology-specific IP integration, such as SRAM, eFlash, and other 3rd-party IP
- Timing constraint generation for STA
EnSilica can help make sure that your RTL is suitable and optimised for ASIC implementation, and can take on all of the tasks needed to produce a netlist that is ready for physical implementation.