Physical Design

The process of generating the ASIC physical design mask data (GDSII) from the Netlist is a critical step in the ASIC development flow. Our team of experienced place-and-route engineers work with the latest EDA tools to optimise the performance, power, and area of your design before preparing the GDSII for foundry tapeout.

We can support a full range of design involvement from small digital hard-macro generation to full turn-key ASIC development.

We work with scripted design flows and can create customised flows to suit specific requirements, if needed.

Physical Design Services

  • Floorplanning

    Whether implementing a single hard-macro block or a full hierarchical ASIC design, careful floorplanning is needed to ensure that the design will not suffer from placement-related routing and timing problems further down the flow.

    EnSilica’s engineers will analyse the architecture, hierarchy, and connectivity of a design and then derive an optimised floorplan that becomes the starting point for the place-and-route steps.

    It is also important to understand any special requirements for the integration of Mixed-Signal IP into the design, such as high-speed SerDes PHYs, PLLs, and ADC/DAC. EnSilica work closely with the  IP vendors to ensure that these components are properly integrated within the design and that their functionality and performance is maintained.

    For full ASIC designs we will also construct the IO and power-delivery structures needed to meet signal integrity, power integrity, and ESD requirements, and will co-design with the packaging team to ensure that the floorplan is compatible with the packaging requirements.

  • Place-and-Route

    This is the main construction step in the physical design flow, and is critical to achieving optimum performance, power, and area. The place-and-route flow used to be mainly timing-driven, but now the constraints are becoming more and more complex to account for low-power requirements, multiple timing modes, noise and power-delivery effects, and ever-increasing physical design-rule complexity.

    Understanding how to get the best from the EDA tools is also important. Generic EDA flows are OK for average designs, but our engineers are often faced with some real challenges that need in-depth tool knowledge and some custom scripting to overcome.

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