Advances in ASIC technology continue to open up new opportunities but they also present new challenges.

Good quality HDL code ensures good quality of results from synthesis and facilitates efficient reuse. EnSilica has extensive experience in creating a broad range of designs using both Verilog and VHDL, based upon a robust set of coding guidelines.

We have extensive expertise in low-power design techniques and are skilled in IP integration and design for reuse methodology. Our highly productive design team has proven ability in taking designs from specification through to fully verified RTL.

The ability to develop a high quality verification strategy is one of the key activities that will determine the success of your ASIC project. Get it wrong and you are looking at a silicon re-spin with typically a 6 - 12months delay in getting your product to market with substantial cost and revenue implications.

EnSilica can help identify the right verification strategy for your design, one that will provide high confidence that the functional requirements defined in the specification are indeed implemented correctly.

Some of the methodologies and techniques we employ are:

• Verification planning and testbench development
• Advanced techniques:
  • UVM, OVM, System-Verilog
  • eRM, e
  • Assertion-based verification using SVA
  • Coverage driven verification
• Regression management etc
• Behavioural modelling : MATLAB, System-C / C++
• FPGA prototyping - emulations and system demonstrators
• Low-power verification techniques - power estimation, CPF/UPF
• Register abstraction based flow enabling design and verification reuse
• Design of always-on agents and protocol checkers
• Cycle accurate C modelling of module and complete systems
• Use of PLI for co-simulation of embedded processors

EnSilica are members of the Mentor Graphics Questa Vanguard Program (QVP) and Cadence Verification Alliance Program

EnSilica have all the expertise needed to support the logical implementation of your design (Synthesis, DFT / ATPG, STA, Formal verification) and interface with your chosen layout team - this could be EnSilica, in-house team, 3rd party layout company or an ASIC vendor

Synthesis
Development of synthesis scripts to target the design onto a specific ASIC technology.

DFT / ATPG
EnSilica have expertise in developing a complete test strategy for your ASIC design to deliver high fault coverage. This includes

• Scan / ATPG
• RAMBIST
• Testing of embedded IP (e.g hard IP / Analogue)
• JTAG

STA / Timing Closure
EnSilica can develop complete timing constraints to support timing driven place & route tools and full Static Timing Analysis on the post-layout netlist, to confirm that the design meets the required performance targets prior to tapeout. We are skilled at working closely with the layout team to achieve efficient timing closure on technologies down to 65nm.

Formal verification
EnSilica undertake formal verificationto confirm logical equivalence between RTL and the synthesised netlist and then gate-gate checking on any subsequent versions of the design as it goes through the design flow ( DFT, physical optimisation etc)

EnSilica can support the physical implementation (Floorplanning, Clock Tree Synthesis, Place & route, Timing Closure and Physical verification) of your design all the way through to generation of GDSII.

With detailed knowledge about the design gained through the design and verification activities, EnSilica are perfectly placed to undertake the physical implementation and ensure that your design reaches tapeout as quickly as possible.

EnSilica work closely with all the major ASIC EDA vendors to support our customer projects. We can adopt the preferred tools and design flow of our customers or develop a specific flow based on our wide experience of the different tools in the market and selecting those which are particularly appropriate for a given design.

Examples of EDA tools used at EnSilica:

Simulation / Verification

• Cadence Incisive Simulator
• Mentor Graphics Questa / Modelsim
• Synopsys VCS

Verification Planning / Tracking

• Jasper Gameplan
• Cadence Verification Manager

ASIC

• Synopsys
  • Design Compiler
  • DFT Compiler
  • Formality
  • TetraMax
  • PrimeTime
• Cadence
  • First Encounter
• Mentor
  • TestKompress
  • Fastscan
  • DFT Advisor

Bug / Issue Tracker

• Bug Genie

Data Management

• Subversion SVN
• Cognidox

EnSilica have experience of working with a wide range of silicon technologies from all the major ASIC vendors and foundries.

Recent projects have used technology from TSMC, Samsung and UMC, at geometries down to 65nm.