Careers

EnSilica is all about the people we employ; people who not only have immense engineering talent, but the drive and enthusiasm to apply it across a diverse range of challenging projects.

If you currently work in ASIC development and are ready to take your next career step then please send us your details. We are always looking for the brightest and best engineers in the country – people who can really make a difference.

Information for recruitment agencies

Please note that EnSilica does not accept unsolicited CVs or sales calls. Agencies should, therefore, not contact us on a speculative basis.

ENS170503-SRASIC : SENIOR ASIC DESIGN ENGINEER (Wokingham)

Job Reference:

ENS170503-SRASIC : SENIOR ASIC DESIGN ENGINEER (Wokingham)

The Role :

The ideal candidate will have a broad skill set covering ASIC design and embedded systems. That includes an understanding of embedded system design on a Zynq platform using Xilinx Vivado, integrating IP with a bus based AXI/Avalon architecture, and debugging on the hardware using Chipscope and development boards. The candidate should be comfortable developing C code for a bare metal application or Linux operating system and have an understanding of how data is efficiently exchanged between the processor and logic sub-systems. Candidate should be comfortable coding signal processing algorithms from C or MATLAB.

The key responsibilities and experience are summarized below:

Responsibilities :

  • RTL design (VHDL or Verilog) of modules from specification, C/C++ or MATLAB
  • Driving Vivado tools and Questasim for simulation.
  • Targeting Xilinx FPGA devices.
  • Generate IP using Xilinx IP Integrator.
  • Building embedded bus systems in Xilinx IP Integrator.
  • Debug hardware containing FPGAs using bench test equipment or Chipscope.
  • Configuring and booting Linux for embedded systems.
  • Writing C code for device drivers

Key Skills / Background :

  • 1st or 2.1 Electronics, Physics or Computer Science from a Tier 1 University.
  • 5+ years’ experience in industry.
  • Strong FPGA tools knowledge including timing closure for FPGAs.
  • Strong FPGA device knowledge including 3 rd party IP availability.
  • Implementation of signal processing algorithms from C or MATLAB.
  • Zynq SoCs using embedded processors ARM.
  • Bench testing and debugging hardware problems.

Personal Skills :

  • Excellent communication and interpersonal skills.
  • Strong and effective presentation skills, able to operate at multiple levels including senior management.
  • Self-motivated.
  • Take ownership of problems.
  • Creative problem solving.
  • Team player

ENS170503-SRALGO : SENIOR ALGORITHAM DESIGN ENGINEER (Wokingham)

Job Reference:

ENS170503-SRALGO : SENIOR ALGORITHAM DESIGN ENGINEER (Wokingham)

The role :

The ideal candidate will have a PhD in Communications Systems or RADAR and have at least 5 years’ experience in industry working on simulating physical layer algorithms, e.g. OFDM or RADAR signal processing. The candidate should have customer facing experience and excellent communication skills both written and oral.

The key responsibilities and experience are summarized below:

Key tasks / responsibilities  :

  • Working within a small Systems Engineering Team
  • Building and enhancing link level simulations
  • Evaluating physical layer algorithms from the technical literature
  • Report writing and giving presentations at industry events
  • Close working with Customer
  • Report to Technical Director

Key skills / Background :

  • 1st or 2.1 Electronics, Physics or Computer Science from a Tier 1 University
  • MSc or Ph.D in Communications, signal processing etc.
  • 5+ years’ experience in industry simulating or designing DSP algorithms for wireless communications systems or RADAR
  • Knowledge of Wireless physical layer algorithms – e.g. MIMO detection
  • Knowledge of RADAR modulation, coding, tracking, e.g. Kalman filter
  • Strong C++
  • Strong MATLAB
  • Understanding of Floating point to fixed point conversion
  • Appreciation of targeting signal processing at FPGA or ASIC technology
  • Some hardware design/verification experience

Personal skills :

  • Excellent communication and interpersonal skills
  • Strong and effective presentation skills, able to operate at multiple levels including senior management
  • Self-motivated
  • Take ownership of problems
  • Creative problem solving
  • Team player

ENS161108-GMVERIF : VERIFICATION GROUP MANAGER (INDIA)

Job Reference:

ENS161108-GMVERIF : VERIFICATION GROUP MANAGER (INDIA)

The Role :

We are seeking an experienced Verification Group Manager to support our custom integrated circuit design and supply business. The candidate must be able to demonstrate a track record of delivering right first time SoC projects.

The candidate will be responsible for defining and delivering the overall functional verification strategy across the organization and responsible for ensuring the functional correctness of our SoC developments.

The key responsibilities and experience are summarized below:

Responsibilities :

  • Provide strong technical and team leadership to verification and validation engineers across all sites recruiting and developing verification lead engineers to support your work.
  • Drive the functional verification and silicon validation of strategy of complex mixed signal SoCs often using one or more embedded processors, advanced power management and 3rd party IPs.
  • Develop a culture of continues improvement, encouraging internal information sharing sessions, industry presentations, feeding back improvements and new ideas into a documented verification flow.
  • Build a collaborative environment across our different sites as well as with customers and EDA vendors to deliver the best technical solutions within the commercial and time constraints of the project.
  • Provide clear and accurate verification status at the required level of detail to each project stockholders including the customer, project manager, project lead and senior management.

Key Skills / Background :

  • Proven track record of managed and successfully delivering multiple SoC projects including mixed mode designs.
  • Experience of manage verification teams of more than 20 engineers
  • Willingness to travel between multiple sites
  • A pragmatic approach to verification which includes a detailed hands-on knowledge of UVM methodologies using SV, formal verification and directed testing.
  • Understanding of verification methodology for mixed mode devices using methods like Verilog-AMS, real number or Verilog behavioural modelling.
  • Understanding of how to apply verification strategy to FPGA based emulation and post silicon validation.
  • Must have excellent interpersonal communication skills and ability to work in a team and lead others.

The ability to efficiently manage your time and proactively drive multiple projects over multiple locations will be key success factor.

ENSI160329-JRVERIF : VERIFICATION ENGINEER (INDIA)

Job Reference: ENSI160329-JRVERIF

The role :

As part of our ongoing expansion, EnSilica India need to strengthen our verification team. We are looking for bright candidates who have an enthusiasm and aptitude for working in this vital part of our business.

With 3-5 years’ experience in industry you will relish the opportunity of working on a diverse range of projects that will both challenge and develop your verification skills.

You will have a good understanding of the key concepts behind advanced verification with experience of writing SystemVerilog and using UVM. You will be comfortable with constrained random verification methodologies, code coverage analysis and running regression tests and understand the importance of monitoring key metrics to assess progress and predict the end-point for the verification process.

Faced with a new project, you will have the ability to work within a team to help deliver a robust and high quality solution.

Ideally you will be familiar with Synopsys VCS & Mentor Questa tools.

The key responsibilities and experience are summarized below:

Key tasks / responsibilities :

  • Verification specialist working on customer and internal projects
  • Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods
  • Active participation in the verification community to drive the introduction of new and effective techniques within our business – to help solve the verification challenges faced by our customers
  • Close working with our customers to build a strong relationship that results in repeat business

Key skills / Background :

  • BE / ME from reputed College / University
  • 3-5 Years’ experience in industry working on a variety of verification projects
  • Knowledge of verification methodologies particularly UVM and SystemVerilog.
  • Demonstrate experience in the implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog
  • Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests
  • Good customer facing skills

Personal skills :

  • Excellent communication and interpersonal skills
  • Strong and effective presentation skills, able to operate at multiple levels including senior management
  • Self-motivated
  • Take ownership of problems
  • Creative problem solving
  • Team player

ENSI160329-SRVERIF : SENIOR VERIFICATION ENGINEER (INDIA)

Job Reference: ENSI160329-SRVERIF

The role :

As part of our ongoing expansion, EnSilica India need to strengthen our verification team. We are looking for bright candidates who have an enthusiasm and aptitude for working in this vital part of our business.

With 5-8 years’ experience in industry you will relish the opportunity of working on a diverse range of projects that will both challenge and develop your verification skills.

You will have a good understanding of the key concepts behind advanced verification with experience of writing SystemVerilog and using UVM. You will be comfortable with constrained random verification methodologies, code coverage analysis and running regression tests and understand the importance of monitoring key metrics to assess progress and predict the end-point for the verification process.

Faced with a new project, you will have the ability to work within a team to help deliver a robust and high quality solution.

Ideally you will be familiar with Synopsys VCS & Mentor Questa tools.

The key responsibilities and experience are summarized below:

Key tasks / responsibilities :

  • Verification specialist working on customer and internal projects
  • Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods
  • Active participation in the verification community to drive the introduction of new and effective techniques within our business – to help solve the verification challenges faced by our customers
  • Close working with our customers to build a strong relationship that results in repeat business

Key skills / Background :

  • BE, B Tech / ME / M.Tech from reputed College / University
  • 5-8 Years’ experience in industry working on a variety of verification projects
  • Knowledge of verification methodologies particularly UVM and SystemVerilog
  • Demonstrate experience in the implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog
  • Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests
  • Good Understanding of Ethernet/Fibre channel skills : 40G/100G PCS knowledge, IEEE CL-91 RS-FEC and Any Ethernet PCS expertise
  • Good customer facing skills

Personal skills :

  • Excellent communication and interpersonal skills
  • Strong and effective presentation skills, able to operate at multiple levels including senior management
  • Self-motivated
  • Take ownership of problems
  • Creative problem solving
  • Team player

ENSI160329-SRDSN : SENIOR DESIGN ENGINEER (INDIA)

Job Reference: ENSI160329-SRDSN

The role :

As part of our ongoing expansion, EnSilica India need to strengthen our design team. We are looking for bright candidates who have an enthusiasm and aptitude for working in this vital part of our business.

With 5-8 years’ experience in industry you will relish the opportunity of working on a diverse range of projects that will both challenge and develop your verification skills.

You will have a good understanding of the key concepts behind  IP design / SoC Design like RTL design skills, RTL coding, Synthesis, Constraints.

Faced with a new project, you will have the ability to work within a team to help deliver a robust and high quality solution.

The key responsibilities and experience are summarized below:

 Key tasks / responsibilities :

  • RTL design and Implementation Engineer working on customer and internal projects
  • Provide high-class RTL Design support to a wide range of projects using IP / SoC Design techniques
  • Close working with our customers to build a strong relationship that results in repeat business

Key skills / Background :

  • BE, B Tech / ME / M.Tech from reputed College / University
  • 5-8 Years’ experience in industry working on IP Design / SoC Design projects
  • Knowledge of Verilog, System Verilog, Synthesis, defining Constraints, formality checks
  • Good Understanding of Ethernet/Fibre channel skills : 40G/100G PCS knowledge, IEEE CL-91 RS-FEC and Any Ethernet PCS expertise
  • Design skills, RTL coding, Synthesis, Constraints, Formality, spyglass, cadence –LEC check
  • Good customer facing skills

Personal skills :

  • Excellent communication and interpersonal skills
  • Strong and effective presentation skills, able to operate at multiple levels including senior management
  • Self-motivated
  • Take ownership of problems
  • Creative problem solving
  • Team player

ENSI160329-SRPVERIF : PROCESSOR VERIFICATION ENGINEER (INDIA)

Job Reference : ENSI160329-SRPVERIF

The role :

As part of our ongoing expansion, EnSilica India need to strengthen our verification team. We are looking for bright candidates who have an enthusiasm and aptitude for working in this vital part of our business.

With 5-8 years’ experience in industry you will relish the opportunity of working on a diverse range of projects that will both challenge and develop your verification skills.

You will have a good understanding of the key concepts behind advanced verification with experience of writing SystemVerilog and using UVM. You will be comfortable with constrained random verification methodologies, code coverage analysis and running regression tests and understand the importance of monitoring key metrics to assess progress and predict the end-point for the verification process.

Faced with a new project, you will have the ability to work within a team to help deliver a robust and high quality solution.

Ideally you will be familiar with Synopsys VCS & Mentor Questa tools.

The key responsibilities and experience are summarized below :

Key tasks / responsibilities :

  • Verification specialist working on customer and internal projects
  • Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods
  • Active participation in the verification community to drive the introduction of new and effective techniques within our business – to help solve the verification challenges faced by our customers
  • Close working with our customers to build a strong relationship that results in repeat business

Key skills / Background :

  • BE / ME from reputed College / University
  • 5-8 Years’ experience in industry working on a variety of verification projects
  • Knowledge of verification methodologies particularly UVM and SystemVerilog
  • Demonstrate experience in the implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog
  • Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests
  • Good understanding of ARM based subsystem verification
  • Good understanding of ARM processors (Cortex A53, A72, A15, ARM A9, R4 etc.)
  • Good understanding of ARM CoreSight architecture
  • Good understanding of AMBA Bus protocols (CHI, ACE, AXI, AHB, APB)
  • Good customer facing skills

Personal skills :

  • Excellent communication and interpersonal skills
  • Strong and effective presentation skills, able to operate at multiple levels including senior management
  • Self-motivated
  • Take ownership of problems
  • Creative problem solving
  • Team player

ENS160316- SARF : SENIOR ANALOG / RF / MIXED SIGNAL ENGINEERS (Bristol & Oxford)

The Role:

As part of our ongoing expansion, EnSilica need to strengthen our RF, Analogue and mixed-signal IC design team. We are looking for bright candidates who have an enthusiasm and aptitude for working in this vital part of our business.
Working from our Oxford or Bristol offices, the ideal candidate will be self-motivated, have a strong academic record with a sound understanding of design principles, and 5+ years experience in RF, analogue or mixed-signal ASIC/SoC development.

Key Tasks / Responsibilities:

  • Detailed design and simulation of high accuracy RF/analogue/mixed signal IC blocks – e.g. references, amplifiers, filters, DAC/ADC, synthesizer building blocks, VCOs, LNAs, Mixers, PA, power management etc. – as well as the higher level integration of these circuits.
  • Full involvement in circuit design flow from definition and specification to production/IP delivery
  • IC design peer reviewing
  • Top level IC/SoC RF/analogue/mixed-signal performance and functional verification
  • Supervision of circuit physical implementation
  • Involvement with system design and modelling
  • Involvement in silicon evaluation and test
  • Working with a multi-disciplined SoC design teams: including digital, software, production, test and application engineers.
  • Working with marketing and customers

Key Skills / Background:

  • Good Bachelors Degree in Electronic Engineering or related discipline, relevant RF/Analogue/Mixed-Signal IC design MSc or PhD preferred
  • Experience in RFIC/Analogue/Mixed Signal schematic design in CMOS. Low power expertise preferred.
  • > 5 years experience design in RF/analogue/mixed signal circuits, specifically in the following areas:
    • Data converters
    • LNAs & Mixers
    • PA
    • Synthesizer building blocks and oscillators
    • Filters and amplifiers
    • High speed serial interfaces
    • Power management building blocks in low voltage deep submicron CMOS
  • Experience in IC layout and physical implementation
  • Demonstrable experience of multiple full IC/SoC design cycle from definition to volume production;
    • Ideally in at least one of the following standards: Bluetooth/Zigbee/WiFi/WiMax, GSM/3G/LTE, GPS, NFC, HDMI, USB, etc.
  • Experienced in CAD tools:
    • Cadence Virtuoso Platform: RF, analogue and AMS simulation, OCEAN, ADE-XL, Spectre/APS
    • Linux, version control/SVN, Office
  • System design and modelling: Matlab, Octave
  • Hands on knowledge of RF/Analogue/Mixed signal IC evaluation and test
  • Up to date on RF/AMS IC design techniques and design methodologies

Beneficial Skills:

  • Knowledge or experience in RF/AMS IP delivery, DSP, CMOS process/PDK development, EM simulation, RF/AMS production test.

Personal Skills:

  • Excellent communication and interpersonal skills
  • Adaptable
  • Strong/Creative problem solving skills
  • Organised and efficient with demonstrated ability to meet deadlines
  • Good team player
  • Self-motivated
  • Take ownership of problems

ENS160309-PD-SP : PHYSICAL DESIGN ENGINEER (Wokingham or Bristol)

The role :

As part of our ongoing expansion, EnSilica need to strengthen our ASIC Implementation team. We are looking for bright candidates who have an enthusiasm and aptitude for working in this vital part of our business.

The ideal candidate will have a strong academic record and 5-10+ years experience in IC Physical Design (PD) within advanced digital ASIC development flows.

You will be familiar with the challenges of implementing complex ASIC/SoC designs from RTL to tapeout-ready GDSII in process nodes down to at least 28nm.

The candidate should have customer and supplier-facing experience and excellent communication skills.

The key responsibilities and experience are summarized below:

Key tasks / responsibilities  :

  • Take full-flow ownership of all stages of the digital RTL-to-GDSII implementation flow for complex ASIC block-level or full-chip designs
  • Work closely with our customers and other EnSilica teams to deliver projects on-time and to the required quality levels
  • Setup, run, and maintain EDA tool flows, as needed, for each stage of the development flow
  • Keep up to date with all aspects of advanced ASIC implementation methodology and best-practice to ensure that EnSilica’s expertise and services are always current and appropriate for each customer project

Key skills / Background :

  • 1st or 2.1 Electronics, Physics or relevant subject from a Tier 1 group University
  • 5-10+ years’ experience in industry with a strong track record in Physical Implementation gained across several successful ASIC projects, and at process nodes down to and including 16FF
  • Specific skills:
    • Extensive hands-on experience with either Synopsys ICC* or Cadence Encounter for block-level and full-chip design, ideally down to 28nm/16FF.
    • STA and timing closure, including constraint development and verification
    • Power-management implementation using UPF/CPF, including verification and power estimation
    • Power-rail analysis and verification
    • Setup and use of RC extraction flows
    • Ability to setup and run DRC/LVS/ERC/DFM using either Mentor or Synopsys tools
  • Ability to quickly and efficiently solve problems, working both independently and with support from our suppliers and customers where needed

Personal skills :

  • Excellent communication and interpersonal skills
  • Strong and effective presentation skills, able to operate at multiple levels including senior management
  • Self motivated
  • Take ownership of problems
  • Creative problem solving
  • Team player

ENS160309-DFT-SP Senior/Principal Design-For-Test (DFT) Engineer (WOKINGHAM)

Permanent or Contract (x2 positions)

Job Reference ENS160309-DFT-SP

As part of our ongoing expansion, EnSilica need to strengthen our ASIC Implementation team.  We are looking for bright candidates who have an enthusiasm and aptitude for working in this vital part of our business.

The ideal candidate will have a strong academic record and 5-10 years’ experience in Design for Test (DFT) within digital and mixed-signal ASIC/SoC development.

You will be familiar with the challenges of architecting, specifying, and implementing DFT within complex ASIC/SoC designs, most of which include power management, memories, and Analog IP elements such as PLLs, ADC/DAC, and SerDes PHY’s. You will also have experience with automatic and manual test-pattern generation flows, fault coverage analysis, and MBIST implementation.

The candidate should have customer and supplier-facing experience and excellent communication skills.

The key responsibilities and experience are summarized below:

Key tasks / responsibilities  :

  • Take full-flow ownership of all DFT, MBIST, and test-pattern generation for complex digital and mixed-signal ASIC designs on an as-needed basis to meet customer project requirements
  • Provide Test-related consultancy to customers both in the pre-sales and implementation stages.
  • Setup, run, and maintain EDA tool flows relating to DFT, MBIST, and test pattern generation
  • Work closely alongside the EnSilica Front-end and Back-end teams to implement and verify DFT at all stages in the development flow
  • Take responsibility for setting and meeting customer’s fault-coverage expectations and requirements
  • Be the primary interface between EnSilica and any back-end service companies that may be sub-contracted to develop hardware or test programs
  • Generate test specification documentation, as required, for delivery to sub-contractors providing test services
  •  Keep up to date with all aspects of ASIC Test methodology and best-practice to ensure that EnSilica’s expertise and services are always current and appropriate for each customer project

Key skills / Background :

  • 1st or 2.1 Electronics, Physics or relevant subject from a Tier 1 group University
  • 5-10 years’ experience in industry with a strong track record in DFT gained across several successful ASIC projects, and ideally at process nodes down to and including 16FF

Specific skills in DFT implementation:

  • Specification at the architecture level
  • Implementation using tool-based and hand-crafted methods
  • Integration of IP including CPU’s, Analog Macros, and IO PHYs
  • MBIST and memory repair integration
  • Coverage analysis and improvement to meet targets
  • ATPG, as well as manual and semi-automatic TPG, including simulation-based methods
  • Implementation of at-speed test methodologies
  • DFT for power-managed designs
  • Generation of STA and scenario/mode constraints
  • Knowledge of the full Synopsys or Mentor Tessent DFT tool kit(s) would be advantageous, including the use of LEQ, simulators, and STA tools for verification
  • Working knowledge of the complete SoC design flow and associated tools and methodologies to deliver working silicon
  • Experience of RTL and gate-level simulation as applied to DFT verification
  • VHDL/Verilog coding skills
  • Experience working with test service providers is desirable, including test hardware specification, test program specification, test program bring-up and debug, yield analysis and enhancement

Personal skills :

  • Excellent communication and interpersonal skills
  • Strong and effective presentation skills, able to operate at multiple levels including senior management
  • Self-motivated
  • Take ownership of problems
  • Creative problem solving
  • Team player

ENS160308-PVERIF : PRINCIPAL VERIFICATION ENGINEER (Wokingham)

Job Reference:

ENS160308-PVERIF : PRINCIPAL VERIFICATION ENGINEER (Wokingham)

The role :

As part of our ongoing expansion, EnSilica need to strengthen our verification team. We are looking for bright candidates who have an enthusiasm and aptitude for working in this vital part of our business

With 10+ years experience in industry you will relish the opportunity of working on a diverse range of projects that will both challenge and develop your verification skills.

You will have an excellent understanding of different methodologies, but particularly SystemVerilog and UVM. Faced with a new project, you will have the ability to quickly assimilate the verification challenge and help define an effective (and pragmatic) verification strategy and gain the support of the end-customer for the chosen approach. You understand the importance of monitoring key metrics to assess progress and predict the end-point for the verification process.

As you rapidly build your verification skills through engagement on a broad range of projects you will have the opportunity to take on the role of verification lead, with responsibility for architecting the test environment and driving the other team members to deliver the agreed solution.

Ideally you will be familiar with both Mentor Questa and Cadence Incisive tools.

The key responsibilities and experience are summarized below:

Key tasks / responsibilities  :

  • Verification specialist working on customer and internal projects – including as the verification lead.
  • Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods.
  • As a verification lead you would also be responsible for the development of a comprehensive verification strategy and plan, along with the architecting and development of the complete test environment.
  • Active participation in the verification community to drive the introduction of new and effective techniques within our business – to help solve the verification challenges faced by our customers.
  • To support business development by working with potential customers to understand their verification requirements and develop innovative technical solutions to achieve new design wins.
  • Close working with our customers to build a strong relationship that results in repeat business.

Key skills / Background :

  • 1st or 2.1 Electronics, Physics or Computer Science from a Tier 1 group University
  • 10+ years experience in industry working on a variety of verification projects
  • Extensive knowledge of verification methodologies particularly UVM and SystemVerilog
  • Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests
  • Expert in the planning and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog.
  • Experience as verification lead on at least one project.
  • Strong VHDL/Verilog RTL

Personal skills :

  • Excellent communication and interpersonal skills
  • Strong and effective presentation skills, able to operate at multiple levels including senior management
  • Self motivated
  • Take ownership of problems
  • Creative problem solving
  • Team player

ENS160308-SVERIF : SENIOR VERIFICATION ENGINEER (Wokingham)

Job Reference:

ENS160308-SVERIF : SENIOR VERIFICATION ENGINEER (Wokingham)

The role :

As part of our ongoing expansion, EnSilica need to strengthen our verification team. We are looking for bright candidates who have an enthusiasm and aptitude for working in this vital part of our business

With 5-10 years experience in industry you will relish the opportunity of working on a diverse range of projects that will both challenge and develop your verification skills.

You will have a good understanding of different methodologies, but particularly SystemVerilog and UVM. Faced with a new project, you will have the ability to quickly assimilate the verification challenge and help define an effective (and pragmatic) verification strategy and gain the support of the end-customer for the chosen approach. You understand the importance of monitoring key metrics to assess progress and predict the end-point for the verification process.

As you rapidly build your verification skills through engagement on a broad range of projects you will have the opportunity to take on the role of verification lead, with responsibility for architecting the test environment and driving the other team members to deliver the agreed solution.

Ideally you will be familiar with both Mentor Questa and Cadence Incisive tools.

The key responsibilities and experience are summarized below:

Key tasks / responsibilities  :

  • Verification specialist working on customer and internal projects – sometimes as the verification lead.
  • Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods.
  • As a verification lead you would also be responsible for the development of a comprehensive verification strategy and plan, along with the architecting and development of the complete test environment.
  • Active participation in the verification community to drive the introduction of new and effective techniques within our business – to help solve the verification challenges faced by our customers.
  • Close working with our customers to build a strong relationship that results in repeat business.

Key skills / Background :

  • 1st or 2.1 Electronics, Physics or Computer Science from a Tier 1 group University
  • 5-10 years experience in industry working on a variety of verification projects
  • Extensive knowledge of verification methodologies particularly UVM and SystemVerilog
  • Strong experience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog
  • Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests
  • Strong VHDL/Verilog RTL

Personal skills :

  • Excellent communication and interpersonal skills
  • Strong and effective presentation skills, able to operate at multiple levels including senior management
  • Self motivated
  • Take ownership of problems
  • Creative problem solving
  • Team player

ENS160308-JVERIF : VERIFICATION ENGINEER (Wokingham)

Job Reference:

ENS160308-JVERIF : VERIFICATION ENGINEER (Wokingham)

The role :

As part of our ongoing expansion, EnSilica need to strengthen our verification team. We are looking for bright candidates who have an enthusiasm and aptitude for working in this vital part of our business

With 2-5 years experience in industry you will relish the opportunity of working on a diverse range of projects that will both challenge and develop your verification skills.

You will have a good understanding of the key concepts behind advanced verification with experience of writing SystemVerilog and using UVM.You will be comfortable with constrained random verification methodologies, code coverage analysis and running regression tests and understand the importance of monitoring key metrics to assess progress and predict the end-point for the verification process.

Faced with a new project, you will have the ability to work within a team to help deliver a robust and high quality solution

Ideally you will be familiar with both Mentor Questa and Cadence Incisive tools.

The key responsibilities and experience are summarized below:

Key tasks / responsibilities  :

  • Verification specialist working on customer and internal projects.
  • Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods.
  • Active participation in the verification community to drive the introduction of new and effective techniques within our business – to help solve the verification challenges faced by our customers.
  • Close working with our customers to build a strong relationship that results in repeat business.

Key skills / Background :

  • 1st or 2.1 Electronics, Physics or Computer Science from a Tier 1 group University
  • 2-5 years experience in industry working on a variety of verification projects
  • Knowledge of verification methodologies particularly UVM and SystemVerilog
  • Demonstrate experience in the implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog
  • Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests
  • Strong VHDL/Verilog RTL
  • Good customer facing skills

Personal skills :

  • Excellent communication and interpersonal skills
  • Strong and effective presentation skills, able to operate at multiple levels including senior management
  • Self motivated
  • Take ownership of problems
  • Creative problem solving
  • Team player