eSi-Floating Point

The eSi-Floating Point IP cores perform single-precision (32-bit) and double-precision (64-bit) floating-point arithmetic according to the IEEE 754-2008 standard. The following operations and features are supported by the floating point IP to enable math acceleration to be included in both ASIC and FPGA implementations:

  • Addition and subtraction
  • Multiplication
  • Division
  • Square-root
  • Integer to floating-point conversion
  • Floating-point to integer conversion
  • Both signed and unsigned integers are supported
  • Rounding is to the nearest even number
  • Infinities
  • NaNs (Not a number) – both quiet and signalling
  • Denormalized (subnormal) numbers
  • Status flags indicating invalid, divide by zero, overflow, underflow and inexact exceptions
  • Fully pipelined enabling each core to produce one result per clock cycle

The IP cores are delivered in Verilog HDL. The cores are technology independent and are DFT ready. All flip-flops are scannable and are triggered off the rising edge of the clock and no tri-states are used.

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