EnSilica provide a comprehensive range of processor peripherals, each with a standard AMBA APB or AHB interface to simplify SoC integration and connectivity.
The eSi-Connect IP suite provides simple to integrate functions from widely used off-chip serial interfaces such as USB, I2C, SPI and UART to control functions including Timer, Real-time clock, Watchdog and GPIO. The blocks are configurable and provided with low-level software drivers suitable for real-time SoC deployment.
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The I2C slave and master is a 2 wire serial bus interface typically used to control peripherals requiring a low speed and limited control interface, for example an EEPROM. This module supports 100kbps and 400kbps I2C modes as well as 7 and 10-bit addressing and clock stretching.
The eSi-SPI is a Serial Peripheral Interface (SPI). It uses a 4 wire serial bus to implement full-duplex, synchronous, serial communications. The block is software programmable and includes configurability for word size (8 or 16-bits), bit ordering (MSB first / LSB first), clock polarity and phase as well as bit rate.
The eSi-UART core can be used to implement asynchronous serial communications. It is ideally suited for implementing RS232 or ISO7816-3 for smartcard based connectivity. It supports a wide range of software configurable UART settings including 7 or 8 bit data, 1 or 2 stop bits and parity. The module supports ISO7816-3 modes T=0 and T=1 with hardware NACK and retry functionality.
The eSi-EMAC core implements an Ethernet Media Access Controller (MAC), providing access to 10/100Mbps Ethernet networks. It is a highly compact design featuring low gate count and low power making it ideally suited for providing network connectivity to 16 or 32-bit MCUs supporting an AMBA APB Bus or similar interface.
Fully certified peripheral device controller with software stack is available supporting USB2.0 either Full/High Speed or High/Slow Speed operations. The number of end-point are configurable as well as the option for a dedicated AHB DMA controller. A low gate-count and remote wake-up functionality makes it ideal for low-power applications.
The eSi-GPIO is a fully featured GPIO controller, the IP provides bi-directional inputs and outputs, plus optional level/edge detection of each input for generating interrupts and pull-up/down control logic.
The eSi-PS/2 is a PS/2 host interface to communicate with devices such as keyboards and mice.
The eSi-RTC implementation of a real-time clock (RTC) it provides time, calender, calender alarm and periodic alarm functionality.
The eSi-Timer is a software programmable multi-function timer/counter used for system timing functions.
The eSi-PWM is a pulse width modulation waveform generator. Features include a configurable number of PWM channels, runtime programmable duty cycle from 0% to 100% and configurable period.
The eSi-MultichannelTimer is a low gate count multichannel timer. It has the following features; configurable number of channels, counter width and single-shot or continuous mode of operation.
The eSi-Watchdog core can be used to generate an interrupt if a keep-alive sequence isn't written to its control registers at a regular interval. This would typically be used to determine whether a program is running correctly, on the assumption that a program that has crashed would not write the correct sequence. The interrupt output would typically drive either the reset or non-maskable interrupt on the MCU, to restart the program.
The eSi-FIR core can be used to implement general purpose filtering of an external data source. The coefficients are programmable with no restrictions on symmetry. The core supports a time-shared input source for compatibility with multi-channel ADCs. The filter output can be decimated to reduce the data rate.
The eSi-IIR core can be used to implement general purpose filtering of an external data source. The core supports a parameterised set of standard filters with very low resource requirements compared to the equivalent specification FIR filter. The filter output can be decimated to reduce the data rate.
The eSi-SMI core provides a static memory interface, allowing access to off-chip RAM, ROM and FLASH memory devices. It supports a configurable number of data (8/16/32) and address pins and configurable number of banks (1-8). Each bank has programmable settings, including: data width, wait states, write-protect and privilege-level.
The eSi-DMA core can be used to implement memory-to-memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-peripheral block data transfers.
It supports a configurable number of channels and number of peripherals and a programmable byte count, access size, burst length and addressing (incrementing / fixed). The design supports an AMBA 3 AHB-lite slave interface for control register access and an AMBA 3 AHB-lite master interface for data transfers.
The eSi-RSA core provides hardware acceleration to encrypt and decrypt messages using RSA public and private keys up to 4096 bits.
The eSi-SWP MAC core provides access to a smart card using single wire protocol data exchange. It implements the functionality of ETSI TS 102 613 V7.9.0 MAC Layer.
The eSi-TRNG core provides convenient access to 256 bit blocks of true random numbers. Using an all digital architecture based on gathering entropy from many ring oscillators it is fully compliant with NIST 800-22. This IP is only provided as a hard macro in the target technology.
The eSi-I2S core is a high quality implementation of an I2S interface using a standard AMBA AHB bus interface. It can be used to transmit and receive audio data via the I2S protocol.