EnSilica are exhibiting at DAC2015 in San Francisco

 7-11th June 2015

The annual Design Automation Conference is one of the industry’s premier events and EnSilica will be exhibiting for the fifth successive year.

For those who are attending, do drop by our stand (2228) where we will be showcasing some of our customers products based on EnSilica IP. We can also provide an update on the expansion of our  ASIC  development, IP and design services offering :

  • Full turn-key ASIC development capability from specification through to GDSII, with Physical Design expertise down to 28nm.
  • Addition of a highly experienced analog design /layout team with expertise in high speed PHY IP
  • Latest addition to our  eSi-RISC family of processors – the eSi-3260 targeting IoT and ‘always-on’ applications
  • Extension of our eSi-Crypto family of IP to now include ECC, RSA and SHA
  • eSi-Module – a zynq based module available now for immediate delivery
  • Off-shore design services though our Bangalore design centre with focus on advanced verification
  • Embedded electronic design service – bringing together our expertise in FPGA, hardware design and embedded software to deliver highly optimised electronic products.

If you cannot attend DAC 2015, but would like to learn more about our new IP and services, or you have a specific IC design opportunity you would like to discuss with our technical team, then visit our website www.ensilica.com for more information or email us at info@ensilica.com

May 2015

Solomon-Systech endorse eSi-RISC Processor

sol_sysThe solution developed by EnSilica, with its excellent features, has enhanced greatly the functionality of our product. We look forward to joining hands again with the team to develop more high-performance IC solutions

Ken Tsui
Vice PresidentDesign Engineering
Solomon Systech Limited.

Jan 2015

 

About Solomon-Systech:

Solomon Systech Limited is a leading semiconductor company providing display IC products and system solutions on an international basis under its own global brand. Adopting a “fabless” business model, the Group specializes in the design, development and sales of proprietary IC products that enable a wide range of display applications for smartphones, smart TVs and other smart devices including consumer electronic products, portable devices, industrial appliances and green energy.

 

 

 

Testimonial from Semisens

semisenseSemisens could reduce die size and lower power consumption of our touch screen controllers using EnSilica’s IPs. Those devices are now successfully released to the market. Benchmarking performed by one of end customers showed that Semisens touch controller consumes lowest power among touch controllers available in the market. In addition to the value the CPU core, EnSilica’s IP provides ease of integration and verification with other logic blocks. Quick application support of quality apps engineers also made our IC design engineers feel comfortable to work with EnSilica. With all those benefits brought to our chip design, EnSilica is now selected as the sole CPU vendor for Semisens. We are glad that the right partnership made our device achieve the best performance and the highest value in this competitive market.

Dave Lee
SoC Design Manager
May 2014

date-14apr-w75

EnSilica Releases eSi-3260 Processor Core

EnSilica launches eSi-3260 processor core with comprehensive SIMD DSP extensions targeting IoT sensing nodes and always-on applications

Combines advanced DSP features with eSi-RISC’s characteristic low power and
small silicon footprint

ENS023-esi-3260-press-image-wb-medium-bWokingham, UK – 14th April 2015. EnSilica, a leading independent provider of semiconductor IP and services, has added to its family of eSi-RISC processor cores with the launch of the eSi-3260 targeted at IoT sensing nodes and always-on applications. The eSi-3260 combines advanced DSP functionality with the characteristic eSi-RISC small footprint and extremely low power consumption.

The inclusion of a 64-bit precision, fully-pipelined MAC unit makes the eSi-3260 ideal for audio, high accuracy sensor hub, motion control and touch screen applications. In addition to 32-bit data, the MAC unit supports dual 16-bit SIMD (single instruction multiple data) multiply and MAC operations. Uniquely, full complex multiplication is also supported, performing four multiplies and two additions per cycle. The inclusion of saturating and rounding arithmetic, along with instructions to support bit-reversed addressing, provides
excellent FFT acceleration and accuracy.

The eSi-3260 employs a 5-stage pipeline which has been optimized to deliver market-leading performance in mainstream process nodes with frequencies of over 1GHz obtainable in a 28nm process with dynamic power as low as 14μW/MHz. This can be reduced to 3μW/MHz when optimizing the processor for power, rather than frequency. A flexible memory architecture, with either native, AXI or AHB interfaces, allows the inclusion of instruction and data caches as well as tightly coupled memories for running code that is timing critical. The addition of a cache facilitates high-performance operations even when they are run from embedded Flash.

The radix-8 fast divide and square root options enable 32-bit integer division and square root operations to be reduced to six cycles, greatly decreasing the cycle count in sensing operations where these operations are key to the code operation. An optional, fully pipelined single precision floating point capability helps accelerate high dynamic range calculations for applications such as gesture recognition and fingerprint detection. Custom instruction support allows a further level of application acceleration such as IIR and logarithmic DSP operations or cryptographic operations for standards including ECC, RSA, AES and SHA.

“The balance of processing performance, silicon area, low power and DSP functionality provided by the eSi-3260 delivers a distinct technology edge for customers looking to develop complex IoT sensing nodes and devices in what is a highly competitive market,” said Ian Lankshear, CEO of EnSilica.

Adopting the eSi-RISC series of processors for its touch screen controllers, Ken Tsui, Vice President, Design Engineering of Solomon Systech Limited said: “The solution developed by EnSilica, with its excellent features, has enhanced greatly the functionality of our product. We look forward to joining hands again with the team to develop more high-performance IC solutions.”

About EnSilica
EnSilica was founded in 2001 and has a strong track record of success in delivering semiconductor IP and providing ASIC/FPGA design services to semiconductor companies and OEMs worldwide. The company is headquartered in the UK and has offices in India and the USA. The company is a specialist in low-power ASIC design and complex FPGA-based embedded systems including hardware and embedded software development. In addition to providing IP and turnkey ASIC/FPGA development, EnSilica also provides point services to companies with in-house ASIC design teams. These services include system engineering, analog and mixed signal design, and advanced verification using UVM, DFT and physical implementation. For further information about EnSilica, visit http://www.ensilica.com.

About Solomon Systech
Founded in 1999, Solomon Systech Limited is a leading semiconductor company providing display IC products and system solutions on an international basis under its own global brand. Adopting a “fabless” business model, the Group specializes in the design, development and sales of proprietary IC products and system solutions that enable a wide range of display applications for smartphones, smart TVs and other smart devices including consumer electronics products, portable devices, industrial appliances and green energy applications. Solomon Systech (International) Limited’s shares have been listed on the main board of the Stock Exchange of Hong Kong Limited since April 8th, 2004 (stock code: 2878). More information about the Group, its products and services may be obtained at http://www.solomon-systech.com

All trademarks are recognised and are the property of their respective companies.
This press release and any associated images (in high-resolution compressed jpeg format) can be downloaded from www.humbugpr.com.

Media contacts:

Dr. David Wheeler, Technical Director for EnSilica
Tel: +44 (0)1183 217 332. Email: david.wheeler@ensilica.com

Keith Mason, Humbug PR
Tel: +44 (0)1305 849403. Email: keith.mason@humbugpr.com
Ann Williams, Humbug PR
Tel: +44 (0)1305 849402. Email: ann.williams@humbugpr.com

Ref: ENS023

EnSilica Article in Verification Horizons

Flexible UVM Components: Configuring Bus Functional Models

mentor-alliance-logo-2017-aEnSilica Verification Consultant, Gunther Clasen has article published in the Mentor Graphics Verification Horizon Journal. The article ‘Flexible UVM Components : Configuring Bus Functional Models’ shows how to write BFMs in a way that they can be configured like any other UVM component.

date-10jan-w75

eASIC and EnSilica Announce 16-bit and 32-bit Soft Processors for eASIC Nextreme

easic_150_48Santa Clara, CA – January 10, 2014 – eASIC® Corporation, a leading provider of Single Mask Adaptable ASIC™ and EnSilica, a leading independent provider of IC design services and IP today announced the immediate availability of 16-bit (eSi-1600) and 32-bit (eSi-3200) soft processor cores. The eSi-1600 and the eSi-3200 are based on an EnSilica’s eSi-RISC highly versatile microprocessor architecture that can be optimized by application through extensive configuration options and custom instructions.

The eSi-RISC architecture provides the flexibility to define a range of hardware functions that minimize silicon area. On–chip memory requirements are reduced by inter-mixed 16-bit and 32-bit instructions, resulting in high code density without compromising performance. eSi-RISC utilizes the industry standard GNU optimizing C/C++ compiler and Eclipse IDE for rapid software development, and supports efficient debugging through a JTAG interface and hardware breakpoints. The eSi-RISC architecture also supports instruction and data cache options for both the 16 and 32-bit processor and a MMU, Floating Point Unit and DSP extensions.

“EnSilica are delighted to partner with eASIC and make our IP available through eASIC’s eZ-IP Alliance Program” said Philip Faulkner, Director of Projects at EnSilica. “The combination of our low cost, flexible, high performance processors and the fast design and turnaround time of eASIC’s single mask ASIC devices enables customers to overcome the challenge of software versus hardware partitioning across a wide range of applications. We look forward to continuing to expand the portfolio of IP available under the program,” added Faulkner.

“The eSi-RISC processors make an ideal embedded solution for use on our single mask adaptable ASIC devices,” said Jasbinder Bhoot, vice president, worldwide marketing at eASIC Corporation. “The small footprint coupled with the versatile configurations options provides a highly cost optimized and low power solution.

About eASIC

eASIC is a fabless semiconductor company offering breakthrough Single Mask Adaptable ASIC devices aimed at dramatically reducing the overall cost and time-to-production of customized semiconductor devices. Low-cost, high-performance and fast-turn ASIC and System-on-Chip designs are enabled through patented technology utilizing Via-layer customizable routing. This innovative fabric allows eASIC to offer a new generation of ASICs with significantly lower up-front costs than traditional ASICs.
Privately held eASIC Corporation is headquartered in Santa Clara, California. Investors include Khosla Ventures, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, Seagate Technology (NASDAQ:STX) and Evergreen Partners. For more information on eASIC please visit www.easic.com.

EnSilica launches Constant False Alarm Rate (CFAR) IP for automotive driver-assist

CFAR144x101Matched to EnSilica’s pipelined FFT IP core, it frees up the apps processor by presenting a marked up radar image

Wokingham, UK – 18th November 2013. EnSilica, a leading independent provider of IC design services and system solutions, has launched a Constant False Alarm Rate (CFAR) soft IP core for use in situational awareness radar sensors for automotive driver-assist applications. The hardware accelerated CFAR IP is matched to EnSilica’s pipelined FFT IP core and, operating on continuous data at one bin per clock cycle, the combination of cores delivers a substantially reduced data set for analysis by the processor. The development of the CFAR IP also followed the guidelines necessary for integration with devices adhering to the ISO 26262 functional safety standard for road vehicles.

Situational radar sensors can be used in a wide variety of driver-assist applications such as advanced electronic stability control systems, pre-crash impact mitigation, blind spot and lane departure detection, and self-parking. 1D and 2D-CFAR is used in these applications to identify relevant objects or targets from the background clutter of a radar image and tag them for further processing. As driver-assist applications grow in complexity, the challenge is processing all the available data while recognising that a very large percentage of the field of view does not contain relevant objects. The EnSilica CFAR IP coupled with a 2K point FFT can calculate and search over 200,000 Fourier Transforms per second, reducing the radar image to a manageable number of possible objects that are critical to the driver safety.

The highly configurable EnSilica CFAR IP implements all the popular compute intensive algorithms, including GOSCA, GOSGO, GOSSO, CA, GOCA and GOSA, that would normally be applied in software and which involve real-time data transform, sorting and selection. The soft IP can be targeted for implementation in either FPGA or ASIC technologies to address a wide range of market segments.

“All-round vehicle radar is becoming a key component of future vehicle electronic control systems,” said Ian Lankshear, CEO of EnSilica. “The challenge is that it provides a massive amount of real-time data that has to be processed. The combination of our CFAR IP and pipelined FFT IP offloads this to hardware, resulting in extreme data reduction and predictable latency.”

date-08oct-w75

EnSilica and Kili Technology deliver FIPS-compliant secure processor IC

kili_PR_150_92Kili 3.1 dual eSi-3250-based processor with 1MB of embedded Flash, USB and NFC connectivity meets FIPS 140-2 Level 3 requirements and targets secure payment, authentication and identity applications.

Wokingham, UK and Toronto, Canada – 8th October 2013. EnSilica, a leading independent provider of IC design services, system solutions and IP, has announced that it has successfully collaborated with Kili Technology Corporation of Canada on the development of the Kili 3.1 FIPS 140-2 Level 3 (Federal Information Processing Standard) compliant secure processor IC. The Kili 3.1 secure processor IC is designed to meet the stringent requirements of payment, authentication and identity applications and production devices are available now.

Drawing on the IP portfolios of both companies, the joint development has been extensively underpinned by EnSilica’s design services. “The development of the Kili 3.1 secure processor IC is another prime example of how a highly focused fabless semiconductor company can collaborate with us to help bring their ideas to silicon,” said Ian Lankshear, CEO of EnSilica. “As the Internet of Things starts to broaden and really take off, the Kili 3.1 secure processor IC provides a much needed, highly-integrated solution that delivers excellent
security and connectivity features with significant potential savings on the bill of materials (BOM).”

The Kili 3.1 secure processor IC utilizes EnSilica’s high-performance, low-power 32-bit eSi-3250 soft processor core with cryptographic acceleration instructions in Kili Corporation’s patented, dual processor architecture that splits secure functionality between the processors. In addition to supplying the eSi-3250 processors complete with 1MB of embedded Flash, standard interconnect and key peripherals required for the application such as USB, I2C, UART, SPI, Smart Card reader, SWP and TRNG, EnSilica incorporated an additional APB peripheral bus to enable the easy connection of Kili’s own silicon-proven, easily portable security IP including NFC radio and ontroller.

Kili 3.1 enables the implementation of the principal cryptography protocols, including RSA, AES and DES, outside the host environment, such as a PC, laptop, tablet or smartphone. It features advanced security functions including mesh sensor; active shield protection; voltage, temperature clock and physical tamper detection; and protected battery backup of key memory with auto erase as well as encryption acceleration and EMV L1/L2 firmware for both contact and contactless applications. Software stacks for capacitive touch
and Bluetooth LE are also available, greatly reducing the time to market.

“Licensing the eSi-3250 has provided us with real technical advantages compared to other CPU cores and outsourcing the processor sub-system development to EnSilica has helped reduce our IC development time,” said Afshin Rezayee, Founder and Co-President of Kili Technology Corporation. “This has allowed us to focus on our product differentiation and the development of the IP specific to our end applications. The flexible multi-processor architecture has helped us develop novel security features to meet the all-important FIPS security certification. We will continue to use EnSilica’s eSi-RISC cores along with its front-end and physical design services to support our ongoing chip development activities.”

EnSilica and Altera Deliver Successful RRH Design

EnSilica, a leading provider of IC design services and system solutions have recently completed a major project with a Tier 1 mobile communications company, to deliver a world-class Remote Radio Head (RRH) solution based on the Altera’s High End Stratix FPGA technology.

This is another example where EnSilica’s expert knowledge of Altera technology gained through over 10 years of working together (EnSilica are a member of the Altera Design Services Network) can deliver the best possible solution for our customers. For the full details click here

EnSilica Move to New UK Headquarters

To support the continuing growth of EnSilica, we have moved to a new larger headquarters in the UK

The headquarters include a dedicated design centre, laboratory area, high-performance computer facility and extensive IT infrastructure, that will ensure the company remains at the forefront of IC design services.
Our New Address is: West Forest Gate, Wellington Rd, Wokingham, Berks RG40 2AT