Automotive long rangeRadar in Arm based SoC

An automotive Tier 1 approached EnSilica with a requirement of a complex Radar processing SoC developed using an Arm based FPGA. The Tier 1 had intended to use an ASSP in their OEMs new model, but its availability was delayed and would not be ready in time for the OEM’s start of production date. The challenge was to develop, verify, and for the Tier 1 to road test and qualify this state-ofthe- art Radar SoC using one of the smaller AMD UltraScale+ FPGA. To complicate matters this design had to meet a stringent power budget.

EnSilica and the Tier 1 collaborated on system level design and specification developing MATLAB and C system models. First prototype was required for collecting data for field trial and off-line processing, a data-logging system interfacing to four 77GHz RF ICs each supporting 4 Rx channels and 3 Tx channels via MIPI. The FPGA performed a 2D FFT and logged the data. The system was delivered to the customer in less than 8 weeks, taking advantage of our prior art and IP. EnSilica was responsible for all the FPGA programmable logic (PL) design in RTL and lowlevel software drivers. EnSilica's IP was customised to fit the needs of most of the signal processing path and tracking functions. EnSilica was responsible for the verification and functional safety aspects of the PL, whilst also supporting the Tier 1 to develop the system so it met the requirements of ISO26262 ASIL-B. As well as the FPGA implementation, EnSilica developed a bit-exact version to run on a NVIDIA GPU farm accelerated using CUDA®. This ran several times faster than real-time allowing off-line data captured during field trials to be quickly processed Using the ARM compiler, simulator and other tools we were able to co-simulate the hardware/ software split for object identification and tracking, thereby verifying this capability against specification. Advanced debug features in Coresight allowed for breakpoints to be set in a combination of hardware and software domains, enabling complex scenarios to be debugged with ease. Using EnSilica's hardware accelerator IP cores the design and verification was complete within 12 months allowing plenty of time for field trials and automotive qualification of the model before the release of the new vehicle model by the OEM. The new Radar system had enhanced performance and was highly differentiated from their competitors. The customer would not have been able to deliver this differentiation if they had used the Radar ASSP as originally planned.