Sensor interface CryptographicBridge ASIC
A biometric sensor company required a very
low-power bridging ASIC using strong encryption
to securely interface between their sensor and a
mobile phone or laptop host.
The goal was to have 5 μA standby current, the
sensor bridge would wake-up when the external
sensor is activated. A small die size for copackaging
with the sensor, it needed to be lowpower
and support strong encryption between
the sensor and a SPI or USB interface.
The cost sensitive application meant the
customer wanted small silicon area and to use a
royalty free processor core.
Customer Challenge
Customer Challenge
While having a very low standby leakage current,
the systems needed to wake-up periodically and
also in response to interface activity. Received
messages were to be captured by the sensor
and the CPU woken up sufficiently quickly for no
data to be lost.
The very-low standby power requirement meant
that very careful attention needed to be paid to
the implementation of the always-on circuits.
Solution
Solution
A multiple power domain ASIC was required
using an always-on domain having ultra lowpower
oscillator and very low leakage logic
cells and IO pads.
The sensor interface was implemented as a
full custom, transistor-level design, using the
target process technology by EnSilica's in
house analogue design team.
EnSilica provided driver software for all
peripherals. An embedded SSL/TLS library was
ported to the device to set-up the secure
connections with the host over SPI or USB. An
FPGA prototyping platform was developed,
allowing the customer to develop their
application software whilst the ASIC
development was in progress.
As a result, their full software stack was ready
and tested by the time we started
manufacture of the ASIC mask set and first
wafers, and our customer had the
application software running on the ASIC
within a few days of receiving first samples.
ASIC functional blocks
Sleep mode and active mode bandgap and LDOs
Sleep mode and active model oscillators
Custom low-leakage IOs cell and logic cells for implementation of always-on circuits
Power management for multiple power domains
Very low-leakage memories with retention modes
Split power domain SPI interface to allow wake-up from SPI messages
ASIC uses
On-chip eFlash memory
Multiple SRAM instances, each with power mode controls
A royalty-free processor core
USB host interface
EnSilica’s ECDSA, SHA and AES accelerators for the encryption function
EnSilica IP
eS-Crypto including AES, SHA, ECDSA and TRNG
EnSilica LDO, PoR, on-chip oscillatorand other power managementfunctions
3rd Party IP
Royalty 32-bit free processor core and supporting peripherals
USB PHY
USB Controller
eFlash Macro
Low power retentions memories
Low-power standard cell libraries
Check More
Energy harvesting authentication ASIC
Distributed Beamformer for Satellite User Terminals(EN92040)
No results found.