The ideal balance of power, resolution and accuracy in ECG systems depends strongly on the intended use case.
By Ian Lankshear
In the first article of this two-part series, we offered an overview of electrocardiography (ECG) systems and how channel count affects analog-to-digital converter (ADC) selection. Now, we’ll cover ADC use cases and design consideration, starting with ADC architecture and resolution trade-offs.
Capturing ECG signals accurately depends on choosing an appropriate ADC resolution. Typical signal amplitudes fall between 0.5 mV and 5 mV, with bandwidths from around 0.05 Hz to 150 Hz. Successive approximation register (SAR) ADCs are widely adopted because they consume little power.
Increasing resolution beyond 12 bits, though, results in a sharp rise in power consumption. Each additional bit multiplies quantization levels, places greater demands on comparator accuracy, and extends conversion time. In many instances, this also means extra trimming and/or non-standard high-precision devices, driving up overall cost.
In practice, engineers often refer to the effective number of bits (ENOB) to measure system performance, since real-world noise typically reduces the achievable resolution of an ADC. Techniques such as oversampling, dynamic range scaling, and digital calibration can improve ENOB without causing a linear rise in power consumption.
Sigma-delta ADCs and incremental variants
Sigma-delta (ΣΔ) ADCs deliver high resolution by using oversampling and noise shaping techniques. They are ideal for low-bandwidth, high-precision signals like ECG waveforms. When run in steady-state mode, the ADC can usually handle only one input channel.
Incremental ΣΔ ADCs, by contrast, reset after each conversion, which allows them to multiplex across multiple input channels. In addition, they provide predictable latency and a scalable trade-off between resolution and conversion time.
A typical configuration for multi-signal biosensing platforms might include eight channels, sampled at around 1 kSps using incremental ΣΔ ADCs. An ENOB of about 13.5 bits is generally sufficient for standard ECG readings and lower-rate measurements, such as 20 samples per second for temperature or electrochemical sensing. With this type of converter, ENOB can even exceed 15 bits under suitable operating conditions.
Analog front-end integration
Given the low amplitude of cardiac signals, effective analog conditioning is vital ahead of digitization. The analog front end (AFE) combines instrumentation amplifiers, filters, and gain stages, all designed to reduce noise and enhance common-mode rejection.
Integrating both AFE and ADC into the application-specific integrated circuits (ASIC) offers notable advantages:
- Reduced parasitics: On-chip coupling helps cut down noise pickup and improves stability.
- Optimized gain scaling: Precise matching enables a smaller ADC dynamic range, which lowers power consumption.
- Improved noise immunity: Filtering out mains interference (50/60 Hz) and motion artifacts is crucial, particularly for wearable and veterinary applications.
Veterinary ECGs face added challenges, as muscle tremors, shivering and motion artifacts can easily dominate the signal. Smaller animals such as cats and exotic species produce lower QRS amplitudes, which require very high-resolution converters and strong interference rejection.
Challenges in fetal ECG monitoring
Mayo Clinic researchers are investigating the use of artificial intelligence tools and ECGs to screen for heart weakness before pregnancy. [Photo courtesy of Mayo Clinic]
Fetal ECG (fECG) acquisition is one of the most challenging use cases. Noninvasive maternal abdominal recordings typically include fetal signals below <50 μV, hidden beneath maternal ECG signals that can be five to ten times stronger and further complicated by substantial noise. Extracting the fetal waveform therefore demands a dynamic range greater than 100 dB.
Incremental ΣΔ ADCs with >16-bit resolution, paired with low-noise AFEs and real-time digital filtering, are well suited for this purpose. Multichannel synchronization and adaptive noise suppression algorithms play a crucial role. Custom ASICs can deliver both the precision analog front-end and the real-time processing pipeline necessary to achieve clinical-grade performance.
Smart watches and rings as a new form factor
Beyond conventional electrode placements, smart rings and watches are becoming practical and popular form factors for single-lead ECG measurement, typically replicating the Lead I configuration.
In smart rings, one electrode touches the inner surface of the finger while the opposite hand contacts a second electrode. In watches, the back electrode rests on the wrist while a finger from the other hand touches a bezel or crown electrode, completing the arm-to-chest circuit.
Both designs produce lower amplitude signals than chest leads and are more vulnerable to motion artifacts. This makes a carefully designed analog front end (AFE) with low-noise amplification, strong common-mode rejection, and adaptive filtering essential.
Because of strict limits on size and battery life, the AFE, ADC, and digital processing stages are now often integrated into a single, low-power custom ASIC. Although they provide only single-lead perspectives, these wearables allow continuous rhythm tracking and early detection of arrhythmias, balancing clinical usefulness with compact, efficient design.
Tailoring ADCs to use cases
Designing an ADC around the specific requirements of its intended application can yield substantial power savings and performance gains. The optimal approach varies depending on the use case.
For wearable devices, efficiency is paramount. Techniques such as duty cycling, adaptive resolution control, and power gating during idle periods help extend battery life without compromising measurement accuracy.
In continuous monitoring systems, where uninterrupted data capture is essential, the ADC must deliver moderate-to-high resolution while maintaining tight control over thermal and power management.
Diagnostic systems, by contrast, demand the highest possible resolution and a wide dynamic range, which are best achieved using ΣΔ architectures.
Multi-sensor platforms often integrate ECG alongside temperature, respiration, or electrochemical sensing, so they benefit from flexible and adaptable ADC architectures.
A tailored ASIC approach enables a single ADC architecture to be reused across multiple sensor types, saving chip area and simplifying overall system integration. It also adds flexibility for second-source options, allowing the ASIC to support different Bluetooth Low Energy or microcontroller unit platforms via standardized interface abstraction.
Healthcare devices often need to measure several vital signs beyond ECG, with multiple sensors multiplexed through the ASIC. The list below summarizes the main use cases and their preferred ADC implementations:
Wearable ECG (spot-check)
Preferred ADC type: SAR
Resolution requirement (ENOB): >10 bits
Sampling rate: 250–500 Hz
Notes: Well-suited to low-duty monitoring and brief measurement periods
Continuous ECG (Holter monitor)
Preferred ADC type: Incremental ΣΔ
Resolution requirement (ENOB): >13.5 bits
Sampling rate: 1 kSps
Notes: Balances continuous high-resolution recording with manageable power use
Fetal ECG (noninvasive)
Preferred ADC type: High-resolution ΣΔ
Resolution requirement (ENOB): 16 bits
Sampling rate:500 Hz – 1 kHz (multi-channel)
Notes: Needs a high dynamic range; highly sensitive to maternal signal interference
Electrochemical sensing (lateral flow)
Preferred ADC type: Incremental ΣΔ
Resolution requirement (ENOB): >15 bits
Sampling rate: 10–50 Sps
Notes: Low bandwidth permits slower sampling while maintaining high resolution
Respiration monitoring
Preferred ADC type: SAR or ΣΔ
Resolution requirement (ENOB): >12 bits
Sampling rate: 100–250 Hz
Notes: Moderate resolution and bandwidth make either ADC type suitable
Temperature monitoring (ambient/body)
Preferred ADC type: SAR
Resolution requirement (ENOB): 10–12 bits
Sampling rate: 1–10 Sps
Notes: Very low power priority is key; SAR is sufficient
Conclusion
The ideal balance of power, resolution and accuracy in ECG systems depends strongly on the intended use case. Standard ADC components seldom provide enough flexibility to meet the conflicting needs of today’s medical designs. Custom ASIC design allows engineers to fine-tune AFE gain, ADC resolution, digital filtering, and power management so they align precisely with target clinical requirements.
Custom incremental ΣΔ ADCs achieve high ENOB at different sampling rates while maintaining exceptional energy efficiency. Integrated AFEs improve measurement quality even further, while nearby filtering and digital logic minimize microcontroller wakeups and reduce processing load.
Adopting ASICs gives medical designers a reliable path to achieve robust, low-power measurements. With this approach, teams gain the benefits of tailored hardware, software-defined flexibility, easier platform reuse, and long-term manufacturability, all key advantages for future connected healthcare systems.
The article has first been published at www.medicaldesignandoutsourcing.com/ on December 2, 2025.
