April 16, 2025
News

EnSilica News & Insights Article

EnSilica News & Insights Article

Munich, Germany and Oxford, United Kingdom

Codasip, a leading provider of functional safety (ISO26262) and cybersecurity (ISO21434) RISC-V CPUs, and EnSilica, a leading provider of mixed-signal and digital ASICs (Application-Specific Integrated Circuits), today announced a strategic licensing agreement of Codasip’s CHERI-enabled (Capability Hardware Enhanced RISC Instructions) embedded CPU IP product from its proven 700 family of cores. EnSilica will integrate the CPU into its recently announced quantum-resilient commercial-off-the-shelf (COTS) processor device. This chip will be generally available through standard distribution channels.

The new COTS device is designed for deployment at the cyber-physical boundary, where state-of-the-art security is paramount. For use in defence, industrial, automotive, and aerospace markets, these systems must achieve the highest levels of resilience. CHERI provides a step-change in security by deterministically removing the memory-safety vulnerabilities that are all too common in networked devices and enabling performant fine-grained compartmentalisation of software.

Codasip, as the leading supplier of commercial CHERI-RISC-V processors, is a founding member of the CHERI Alliance. The company’s engineers have been instrumental in defining the CHERI-RISC-V specification and creating a wide range of commercial embedded cores, receiving numerous awards for this work.

Dr Ron Black, CEO of Codasip, said: “Our strategic partnership with EnSilica is already gaining momentum as we work together to unlock the full potential of our leading-edge 32-bit and 64-bit CHERI-RISC-V CPUs. This first business partnership with EnSilica around our CHERI-RISC-V embedded processor marks an exciting milestone. CHERI is a game-changing technology and brings huge potential to work on further business opportunities in the future.”

Ian Lankshear, CEO of EnSilica, added:

“Partnering with Codasip allows us to bring commercial-grade CHERI-enabled security into our next-generation secure quantum-resilient microcontroller. This collaboration strengthens our ability to deliver functionally safe and cyber-resilient silicon for long-lifecycle applications that demand the highest levels of trust and assurance.”

Check more

Largest UK Tiny Tapeout workshop at University of Sheffield brings hands-on chip design to 120+ students

Largest UK Tiny Tapeout workshop at University of Sheffield brings hands-on chip design to 120+ students

Sheffield, UK – May 5, 2026– The School of Electrical and Electronic Engineering at the University of Sheffield ...
EnSilica at TSMC 2026 NA Technology Symposium

EnSilica at TSMC 2026 NA Technology Symposium

Join us EnSilica at TSMC 2026 NA Technology Symposium on 22 April!Silicon innovation is expanding AI to ...
No results found.

Explore more news & insights from EnSilica