EDA Tools

EnSilica is experienced in using a wide range of best in class EDA tools to improve the quality and efficiency of IC design, verification and test.  The EDA tools we typically use in both our Custom ASIC Design and full-flow IC/ASIC Design Services include:

  • Design Control
Version control (SVN based for documents, RTL & Virtuoso OA)
  • Regression
Jenkins/ Cadence vManager
  • System Design
Mathworks Matlab / GNU Octave, Excel, Verilog
  • RF, Analog & MS Environment
Cadence Virtuoso System Design Platform (incl. Composer, Explorer, Assembler, Layout G/XL)
  • RF, Analog & MS Simulation
Cadence Spectre Platform , Mentor Analog FastSPICE (AFS) Platform and Keysight Advanced Design System (ADS)
  • Electro-Magnetic simulation
Keysight Momentum FEM
  • Digital Simulation
Mentor Questa, Cadence Incisive Enterprise Simulator and Xcelium Parallel Logic Simulation
  • Verification planning
Excel / Cadence vManager
  • Linting / CDC
Mentor Questa CDC, Cadence HAL
  • Synthesis
Synopsys DC Ultra, Power Compiler, Test Compiler
  • UPF Verification
Synopsys Verdi Suite
  • Place & Route
Cadence Virtuoso Digital Implementation / Innovus and Synopsys IC Compiler II
  • DFT
Mentor Tessent
  • Layout Extraction
Mentor Calibre PEX (analog)/Synopsys StarRC (digital)
  • Digital Sign-off Timing
Synopsys PrimeTime
  • Logic Equivalence
Synopsys Formality
  • Timing Library Generation
Cadence Liberate
  • Power EMIR analysis
Cadence Voltus
  • Physical Verification
Mentor Calibre (DRC/ERC/LVS)
  • PCB Design and layout
Altium Designer
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