EDA Tools

EnSilica is experienced in using a wide range of best in class EDA tools to improve the quality and efficiency of IC design, verification and test.  The EDA tools we typically use in both our Custom ASIC Design and full-flow IC/ASIC Design Services include:

  • Design Control
SVN and ClioSoft
  • Document Control
  • Requirements Capture
Sparx Systems Enterprise Architect
  • Regression
Jenkins/ Cadence vManager
  • System Design
Mathworks Matlab / GNU Octave, Excel, Verilog
  • Analog Environment
Cadence Virtuoso IC (Composer, ADE-XL, LayoutXL)
  • RF/Analog/MS Simulation
Cadence Spectre/ MMSIM, Mentor AFS/Symphony, Keysight ADS
  • Electro-Magnetic simulation
Keysight RFpro, Momentum & FEM, Ansys HFSS
  • Digital Simulation
Mentor Questa, Cadence Xcelium Simulator
  • Verification planning
Excel / Cadence vManager
  • Linting / CDC
Questa CDC, Cadence HAL
  • Synthesis
Synopsys Design Compler Ultra & Cadence Genus Synthesis Solution
  • UPF Verification
Synopsys Verdi Suite
  • Place & Route
Cadence Innovus and Synopsys IC Compiler II
  • DFT
Mentor Tessent
  • Layout Extraction
Mentor Calibre PEX (analog), Synopsys StarRC (digital)
  • Digital Sign-off Timing
Synopsys PrimeTime
  • Power/Thermal Analysis
Cadence Voltus
  • Logic Equivalence
Synopsys Formality and Cadence Conformal
  • Physcial Verification
Mentor Calibre DRC/ERC/LVS
  • PCB Design and layout
Altium Designer
  • Yield Analysis