eSi-Comms

• Parameterisable and configurable to serve a wide diversity of modern air interface standards.
• Simple streaming interfaces supporting dataflow.
• Register interface for configuration.
• Synchronization in time, frequency and phase through advanced DSP algorithms and control loops.
• Maximum likelihood equalization of single and multicarrier systems.
• Demodulation for BPSK up to 1024-QAM with soft decision bit-metric generation.
• Reed-Solomon and soft-decision Viterbi error correction decoding.
• Multiple antenna receiver processing.
• Silicon proven Digital Front End (DFE) IPs, including fractional and CIC sample rate converters, NCO for digital up/down conversion, CFR for peak-limiting, adaptive DPD for PA linearisation, equaliser, I/Q and DC offset correction units.
• Standards include 4G, 5G, 5G NTN, 802.11a/n (Wi-Fi), DVB-T(2), DVB-S(2), DVB-C(2), DAB, Li-Fi,  DRM, UWB, LTE.
• Applications include wireless sensors, remote metering, cellular, wireless LAN and broadcast products.

• Advanced DSP algorithms for robust communication links.
• Integrated by our expert team.
• Backed up by the EnSilica reputation for quality design services.

The eSi-Comms IP is available through our Design Services to speed up your time to market and reduce risk. We can provide you with C, SystemC, CUDA or MATLAB libraries of the IP blocks for your evaluation and integration into your system design tool-chain. Once the final transceiver design is agreed EnSilica will parameterise and configure the IP, delivering your custom variation optimised for power and area. Optionally we can take ownership of the whole ASIC or FPGA development.

We provide a consultancy service for custom transceiver designs, where the synchronization, equalization and channel coding are simulated to find the effects of analog impairments, noise and channel effects, such as multipath and correlation. Our experts can advise on the right signal processing to deal with these impairments, and design the hardware to suit.

The trend for communications is ever more towards a flexible software defined radio (SDR) based modem. To support this approach many of the eSi-Comms IP blocks are designed to act as hardware accelerators to  processor core such as an Arm core or DSP from Tensilica or Ceva. This provides a unique combination of flexibility together with dedicated hardware engines to off-load compute intensive processing.

Each standard has its own particular variation of the actual processing chain, however they share a common baseline. The diagram below shows the elements of a generic OFDM transmit chain. This identifies the typical processing modules that are found in many popular transmit chains such as IEEE802.11a (Wi-Fi), DVB, DAB,  EnSilica has generic solutions for the baseband modules identified in blue, and for some specific standards like IEEE802.11a/n these are already pre-configured.

EnSilica provides a portfolio of generic OFDM receiver IP blocks. These allow many of the popular communications standards to be built. The IP catalogue is summarised in the diagram below which shows a typical OFDM receiver chain. The exact signal processing line-up may not be exactly as described in this diagram, it is just for illustration.

The block diagram below illustrates a reference Tx DFE architecture in a multi-band 4G/5G processing chain.

Input I/Q data streams originating from the MODEM may have different bandwidths and associated sampling rates. The combination of the Fractional and CIC SRC filters equalize the sampling rates and scale them up, in order to shift to the required frequency offsets by the NCOs. The Fractional SRC and NCO can also be used for fine delay and phase balancing, respectively, in phased array applications.

The combined data channels are fed into the CFR block for peak-limiting, followed by the adaptive DPD for linearizing the PA. The equalizer and QEC-DC blocks serve for correcting linear distortions, I/Q imbalances and DC offsets in the RF.

Depending on the exact system design, additional simple DFE blocks such as Half-Band SRC, Digital Gain Control (DGC) and Power Monitor Units (PMUs) can be inserted in the DSP chain.

The block diagram below illustrates a reference Rx DFE architecture in a multi-band 4G/5G processing chain.

It is observed that the same DSP blocks used in the Tx DFE are re-used in different configuration, for achieving the reverse processing function. Exceptions are the CFR and DPD blocks, which are not required in the Rx DFE.

Again, depending on exact requirements additional simple blocks (HB SRC, DGC, PMU) can be added in the DSP chain.

The entry level for a wireless communication system has high technical barriers. Increasingly the system needs to be designed around readily available IP components, utilising proven DSP algorithms for synchronization, equalization, demodulation and channel decoding. The rationale for using eSi-Comms IP is to speed up development time and reduce risk in final silicon.