eSi-ADAS

Radar processing IP suite  for Advanced Driver Assistance Systems

The EnSilica eSi-ADAS™ is a suite of radar accelerator IP including a complete Radar co-processor engine, they enhance the overall performance and capabilities of radar  systems for automotive, drone and UAV applications that require fast and responsive situational awareness.

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Industry Leading Radar Processing IP Suite

EnSilica Suite of Radar hardware accelerator IPs increase the performance and capability of modern MIMO radar systems. The IP has been licensed by automotive Tier 1s for use in FPGAs and by Tier 2s as the accelerators for Radar baseband ASSPs.  A range of hardware accelerator function are available including the following  :

  • A suite of FFT engines optimised for use in Radar systems  including functionality such as path loss compensation and 4D hypersphere clustering
  • Highly configurable and programmable Constant False Alarm Rate (CFAR) engine support a wide range of CFAR modes including Generalised Ordered Statistic (GOS) and Cell Averaging (CA) modes
  • Kalman Filter (KF) Engine providing hardware acceleration of Extended (non-linear) KF (EKF) with non-linear function transformations and Jacobian matrices computed externally
  • Tracking Engine implementing the control functionality for maintaining the object tracking list using the eSi-KalmanFilter engine
  • Floating point matrix accelerator supporting add/sub, multiply, determinant, RQ decomposition, back substitution, Cholesky decomposition
  • Super resolution engine performing SVD of non-square matrix, as well as MUSIC eigenvector extraction, MinNorm vector extraction and diagonal loading and Capon matrix extraction

The cores have been silicon proven and used in ISO-26262 certified products.

eSi-ADAS MIMO Radar Co-processor

Industry Leading Capabilities

Compared to current ADAS processing methods, the eSi-ADAS Co-processor offers a number of significant benefits:

      • Short and long range radar modes
      • Real-time tracking of hundreds of objects
      • Support for Range, Doppler and Azimuth
      • Offload of radar target processing from the ECU
      • Up to 10x lower power

Ultra Fast, Ultra Small & Ultra Low-Power

The compact, low gate-count architecture of the eSi-ADAS co-processor enables the high bandwidth and computationally intensive operations involved in plot extraction and tracking to be quickly and efficiently processed at the radar receiver stage, significantly reducing the load and overhead on the main ADAS system ECU, CPU or DSP and at the same time boosting overall ADAS capabilities.

Operating on range, velocity and angular measurements eSi-ADAS applies advanced digital processing techniques including 3D Fast Fourier Transforms, burst averaging to improve signal-to-noise ratio, Constant False Alarm (CFAR) detection and Kalman Filtering. These operations all take place in real-time to constantly update hundreds of objects and their associated movement.

To provide the most precise plot extraction eSi-ADAS operates in conjunction with a fast chirp capable RF stage and multiple receive channels. EnSilica has implemented its patented techniques to overcome the disadvantages usually associated with processing fast chirp modulation, notably its high computational and memory requirements.

  • Can process multiple antenna systems with 100s of virtual antennas
  • Uses advanced processing methods such as super resolution – MUSIC, Capon, MinNorm
  • Real time extraction and tracking supporting many hundred of plots
  • Low-latency – track updates in 10s of milliseconds
  • Raw object associated with each detected object is available for external AI based processing
  • Combined LRR and SRR object tracking

FPGA Demonstrator

An FPGA-based module is available to enable the full capabilities of the eSi-ADAS co-processor to be evaluated. EnSilica’s Radar and ASIC experts can provide integration support for other FPGA platforms or design and supply a custom ASIC.

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