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Codasip announces strategic licensing agreement with EnSilica for its CHERI-enabled embedded CPU from the 700 family

Munich, Germany and Oxford, United Kingdom  – November 20, 2025

Codasip, a leading provider of functional safety (ISO26262) and cybersecurity (ISO21434) RISC-V CPUs, and EnSilica, a leading provider of mixed-signal and digital ASICs (Application-Specific Integrated Circuits), today announced a strategic licensing agreement of Codasip’s CHERI-enabled (Capability Hardware Enhanced RISC Instructions) embedded CPU IP product from its proven 700 family of cores. EnSilica will integrate the CPU into its recently announced quantum-resilient commercial-off-the-shelf (COTS) processor device. This chip will be generally available through standard distribution channels.

 

The new COTS device is designed for deployment at the cyber-physical boundary, where state-of-the-art security is paramount. For use in defence, industrial, automotive, and aerospace markets, these systems must achieve the highest levels of resilience. CHERI provides a step-change in security by deterministically removing the memory-safety vulnerabilities that are all too common in networked devices and enabling performant fine-grained compartmentalisation of software.

 

Codasip, as the leading supplier of commercial CHERI-RISC-V processors, is a founding member of the CHERI Alliance. The company’s engineers have been instrumental in defining the CHERI-RISC-V specification and creating a wide range of commercial embedded cores, receiving numerous awards for this work.

 

Dr Ron Black, CEO of Codasip, said: “Our strategic partnership with EnSilica is already gaining momentum as we work together to unlock the full potential of our leading-edge 32-bit and 64-bit CHERI-RISC-V CPUs. This first business partnership with EnSilica around our CHERI-RISC-V embedded processor marks an exciting milestone. CHERI is a game-changing technology and brings huge potential to work on further business opportunities in the future.”

 

Ian Lankshear, CEO of EnSilica, added: “Partnering with Codasip allows us to bring commercial-grade CHERI-enabled security into our next-generation secure quantum-resilient microcontroller. This collaboration strengthens our ability to deliver functionally safe and cyber-resilient silicon for long-lifecycle applications that demand the highest levels of trust and assurance.”

DSIT announcement

 EnSilica to develop quantum-resilient secure processor chip for critical national infrastructure applications backed by £5m UK Government ‘Contract for Innovation’

Oxford, UK, November 13, 2025: EnSilica, a leading provider of mixed-signal ASICs (Application-Specific Integrated Circuits), has been awarded a £5 million ($6.6m USD) ‘Contract for Innovation’ by the UK Government’s Department for Science, Innovation and Technology (DSIT), following a competitive process.

 

Following on from the UK Government’s Digital Security by Design (DSbD) programme, this latest Government funding furthers its ambition to commercialise the availability of Capability Hardware Enhanced RISC Instructions (CHERI), which represents a transformative hardware security architecture designed to mitigate memory safety vulnerabilities, one of the most significant sources of modern cyberattacks.

 

EnSilica’s commercial-off-the-shelf (COTS) CHERI-compliant secure processor chip, developed under the contract, will target next-generation quantum-resilient applications requiring the highest levels of security and functional safety, with relevance across defence, industrial, automotive and aerospace markets. The device will feature a rich set of interfaces tailored for high-integrity industrial and automotive applications, supporting secure connectivity, advanced sensor integration and robust real-time control. It will be developed in line with ISO/SAE 21434 for automotive cybersecurity and ISO 26262 for functional safety, while also meeting the equivalent cybersecurity and functional safety requirements for industrial markets.

 

This programme sits within a wider UK Government initiative to accelerate the commercialisation of advanced hardware security technologies, supported by up to £21 million of national investment. It reflects increasing emphasis on bringing robust, security-focused silicon to market at scale.

 

EnSilica has a strong track record of developing and shipping high-integrity automotive and industrial devices, including ISO 26262 ASIL-D qualified chips now in production with more than ten million units shipped, and has delivered advanced industrial controllers for leading global OEMs, including the industrial programme announced for Siemens earlier this year.

 

The UK Government has identified CHERI as central to strengthening the security of future computing systems, and its continued funding aims to accelerate the development and adoption of secure CHERI-enabled chips with commercial relevance in critical national infrastructure use cases. This innovation aligns with the UK Government’s broader semiconductor strategy, supporting national resilience in cybersecurity and contributing to the growth of the UK’s semiconductor ecosystem.

 

The COTS chip will also include EnSilica’s latest Post Quantum Cryptography (PQC) accelerator IP, making the chip resilient to attacks from quantum computers; a new class of computing system that exploits the principles of quantum mechanics, enabling them to solve certain complex problems, such as cryptographic problems, exponentially faster than today’s processors.

 

Security analysts have raised quantum computers as an emerging security risk with parties capturing encrypted data, with the intention of decrypting it in the future when high-performance quantum computers become more available, a tactic known as ‘harvest now, decrypt later’. The deployment of PQC is therefore essential to future-proof secure processors and communications systems.

 

The PQC market is forecast1 to grow from $310m in 2024 to $9.4bn by 2033 representing a 45% CAGR and driven by regulation and long-lifecycle systems needing future-proof security.

 

EnSilica’s PQC IP enables the development of quantum-resilient secure semiconductors across its core markets of automotive, industrial and satellite communications, ensuring compliance with current and emerging cybersecurity standards. Ownership of this IP provides the company with the ability to deliver deep customisations, auditability and reuse across multiple ASIC programmes, thereby reducing development cost and strengthening EnSilica’s competitiveness.

 

The company has licensed its PQC IP and its other cryptographic IP to one of the world’s leading semiconductor networking companies, providing external validation of the quality of EnSilica’s IP and demonstrating growing market demand for quantum-resilient semiconductors.

 

Prof. John Goodacre, Director of Secure and Resilience Growth at Innovate UK, commented: “EnSilica’s project exemplifies the type of cutting-edge silicon development that positions the UK at the forefront of global hardware security innovation. By supporting the integration of CHERI technology into a mainstream and generally available device, this project will lead to the eradication of significant cyber threats against our critical infrastructures and the increased safety and resilience of commercial products.”

 

Ian Lankshear, Chief Executive Officer of EnSilica, added: “As a leading silicon chip maker, we are delighted to have our secure processor chip chosen by the UK Government for this Contract for Innovation. This will expand our products by offering a CHERI-enabled secure processor chip as a commercial off-the-shelf product, not only putting CHERI-enabled devices into the hands of product developers and strengthening their security capabilities but also contributing to a more robust and resilient UK technology supply chain.”

EnSilica and Codasip announce strategic partnership

EnSilica and Codasip announce strategic partnership to bring CHERI cybersecurity to automotive, critical national infrastructure, defence and aerospace applications  

 

Oxfordshire, United Kingdom and Munich, Germany, – September 18, 2025: EnSilica, a fabless supplier of mixed-signal and digital ASICs, and Codasip, a provider of functionally-safe and cyber-resilient RISC-V CPUs, announces a strategic partnership to enable custom ASICs incorporating CHERI (Capability Hardware Enhanced RISC Instructions), Post-Quantum Cryptographic (PQC) acceleration, and advanced system-level security and safety features. These will serve industrial, automotive, critical national infrastructure, including defence and aerospace applications.

 

CHERI represents a transformative hardware security architecture designed to mitigate memory safety vulnerabilities, one of the most significant sources of modern cyberattacks, and provides fine-grained compartmentalisation to increase software robustness and resilience.

 

EnSilica will use Codasip’s portfolio of 32-bit and 64-bit CHERI RISC-V processors as the foundation for developing customer-specific System-on-Chip (SoC) integrated circuits. These secure platforms will integrate processing, PQC and classical encryption hardware, and tailored analogue and digital functionality to meet the precise requirements of the end application.

 

Ian Lankshear, CEO of EnSilica said: “Cybersecurity has become a defining challenge for automotive, industrial and defence systems, with attacks growing in scale and sophistication. This partnership positions EnSilica at the forefront of delivering cyber-resilient chips that combine CHERI’s hardware-enforced memory safety with post-quantum cryptography. By building on Codasip’s advanced CHERI RISC-V processors, we can offer customers complete, application-specific ASIC solutions with security and functional safety designed in from the ground up. We are excited to work with Codasip to bring this next generation of trusted silicon to market.”

 

Dr Ron Black, CEO of Codasip added: “The partnership will help to unlock the full potential or our leading-edge 32-bit and 64-bit CHERI RISC-V CPUs. Developed in line with ISO 26262 functional safety and ISO 21434 cybersecurity standards, our processors come with a complete ecosystem including CHERI toolchain, CHERI Linux, and CHERI RTOSes. By combining these with EnSilica’s ASIC expertise, we can accelerate the adoption of CHERI-based security in mission-critical applications.”

EnSilica Establishes New EU Mixed-Signal Design Centre in Budapest, Hungary

EnSilica is establishing of a new design centre in Budapest, Hungary.

 

The facility strengthens EnSilica’s presence in the European Union and taps into Budapest’s deep technology ecosystem, which hosts numerous leading automotive and industrial multinationals. This expansion will increase the Group’s global headcount to around 210 employees.

 

By the end of September 2025, the Budapest team will comprise 16 experienced engineers, many with 10 to 20 years’ expertise in mixed-signal chip design. Their technical excellence and collaborative approach are closely aligned with EnSilica’s culture and growth strategy.

 

The centre will focus on developing advanced mixed-signal designs for industrial and automotive applications, providing additional EU-based design capacity to support recent design wins and a strong pipeline of opportunities.

 

EnSilica’s operations now span four UK engineering design centres in Abingdon, Sheffield, Bristol, and Cambridge, alongside international facilities in Bangalore (India), Porto Alegre and Campinas (Brazil), and Budapest (Hungary).

 

Ian Lankshear, Chief Executive Officer of EnSilica, commented: “We are delighted to establish a base in Budapest, a city which has rapidly become a key technology hub in the EU. EnSilica continues to attract exceptionally talented engineers at a time when there is a significant global talent shortage, and this strategic move will allow us to further strengthen our position in our focused market segments to ensure we are ideally placed to capitalise on exciting near-term growth opportunities.”

EnSilica cuts post-quantum cryptography (PQC) silicon area with three-in-one IP block

Oxford, UK, July 21, 2025: EnSilica, a leading maker of mixed-signal ASICs (Application Specific Integrated Circuits), has developed a combined hardware IP block supporting the full CRYSTALS post-quantum cryptography (PQC) suite, saving silicon area, power and cost. The licensable eSi-CRYSTALS PQC accelerator runs Dilithium (FIPS-204), Kyber (FIPS-203) and SHA-3 (FIPS-202) algorithms, which previously required three separate IP blocks.

 

In August 2024, the US National Institute of Standards and Technology (NIST) released the first three finalised PQC standards, with additional algorithms announced or in draft stages. Dilithium, Kyber, and SHA-3 are advanced cryptographic algorithms designed to secure digital systems against both classical and quantum computing threats. Dilithium is used for digital signatures, providing authentication and data integrity, while Kyber is a key encapsulation mechanism that enables secure key exchange. Integrated into the block is also a hardware-optimised implementation of the cryptographic SHA-3 hash function that creates a digital fingerprint of data allowing for robust integrity verification. Together, these algorithms form the foundation for quantum-resistant security in modern systems, ensuring long-term protection of sensitive information.

 

Ian Lankshear, CEO of EnSilica, commented: “The emerging PQC threat is not just theoretical. Security analysts warn that adversaries can already capture encrypted data today, with the intention of decrypting it in the future when quantum capabilities become available, a tactic known as ‘harvest now, decrypt later’. The implications are profound for those relying on today’s cryptographic schemes, which is why EnSilica’s PQC offering delivers future-proof hardware protection at the silicon level with minimal silicon area for mature and advanced technology nodes.”

 

EnSilica previously announced separate Dilithium, Kyber and SHA-3 algorithms licensed for use by a major semiconductor company for a 5 nm networking ASIC. The new IP offers a more compact implementation than separate cores. EnSilica also has a full suite of classical cryptographic accelerators including ECC, ECDSA, RSA, AES, ChaCha20, and Poly1305. In addition, the company offers a NIST-compliant true random number generator (TRNG).

 

EnSilica Presents Innovation in Silicon-Based Satellite Communications at ISCAS 2025

EnSilica was proud to take part in the IEEE ISCAS 2025 conference, held in London this May, where Omotade Iluromi presented during the Industry Innovation Track.

His talk, titled “Closing the Communications Link to Space with Silicon Systems,” explored how modern silicon technologies are enabling transformative advances in satellite communications. The presentation focused on the role of silicon circuits and systems in meeting the challenges of broadband connectivity — from NGSO constellations and ground terminals to direct-to-handset applications.

Omotade also highlighted EnSilica’s ongoing development of low-cost, high-performance satellite communications ASICs, including Ku and Ka-band RFICs and digital beamformer ICs for both ground and satellite applications.

We’re excited to continue pushing the boundaries of what’s possible in space-based communications.

EnSilica establishes new engineering hub in Cambridge, UK

EnSilica, a leading maker of mixed-signal ASICs (Application Specific Integrated Circuits), has announced it has established a new engineering hub in Cambridge, UK.

 

Drawing on Cambridge’s renowned semiconductor ecosystem, EnSilica has opened a new engineering facility in the city and has recruited six engineers, four of whom hold PhDs, increasing the company’s global workforce to 190.

 

With the addition of this new facility and technical expertise, EnSilica will expand its existing mmWave / RF integrated circuit design capabilities, an area in which the company has already seen significant customer demand. The expansion has been facilitated by the recent UK Space Agency C-LEO-funded award, alongside additional contract momentum and customer wins that continue to support the company’s growth.

 

EnSilica currently operates across three UK engineering design centres in Abingdon, Sheffield and Bristol, alongside additional international engineering facilities in Bangalore, India, and Porto Alegre and Campinas in Brazil.

 

Ian Lankshear, Chief Executive Officer of EnSilica, commented: “We are delighted to have not only secured a team of highly skilled engineers at a time when there is a very real shortage of engineering talent in the UK, but also to establish a firm base in an established UK tech hub like Cambridge, which ideally positions the business to attract additional talent. By further expanding our engineering know-how across the satellite and communications market, I believe that this investment will enable the business to capitalise further on very real and near-term growth opportunities.”

 

EnSilica expands satcoms user terminal portfolio with dual-beam, dual-polarization Ku-band analogue beamformer chipset

Oxford, UK, : EnSilica, a leading maker of mixed-signal ASICs, has announced two Ku-band beamformer integrated circuits, the ENS92051 and ENS92052, which offer best-in-class power consumption and performance. They are designed to address the needs of the next generation of electronically steered antennas for a range of user terminals used with LEO, MEO and GEO satellite constellations.

 

The ENS92051 is the dual-beam Ku-band receiver (Rx) supporting eight channels with separate amplitude and phase control. The Rx carrier frequency range is 10.7 to 12.75 GHz.

 

The ENS92052 is the Ku-band transmitter supporting eight channels with separate amplitude and phase control. The Tx carrier frequency range 13.75 to 14.5 GHz.

 

The eight channels of the chipset can support four dual-polarisation or eight single-polarisation elements.  The highly integrated devices offer low-power and low-cost using phase and amplitude controls with a built-in temperature sensor, and the transmitter has an integral power detector.  The chipset includes a beam table to support very low-latency beam switching and supports a range of power-saving modes.

 

The device SPI bus and control pins operate from standard 1.8V logic at speeds up to 50 MHz, the core voltage is 1.0 V.  Both chips come in a 63-pin Wafer Level Chip Scale Package.

 

The devices will be fabricated and tested in Europe, offering customers a European sovereign supply chain. They are designed to meet the requirements of DO-254 DAL 5 and qualified to AEC-Q100 automotive grade 2.

 

Paul Morris, VP of RF & Communication BU commented:

 

“The addition of these Ku-band beamformer ICs to our portfolio enables our customers to develop the lowest power user terminals which can connect to existing constellations such as Eutelsat/OneWeb.  They also boost the European supply chain in satellite communications which has become increasingly important in recent months.”

 

The chipset is available for sampling to lead customers.

 

EnSilica Agrees $18m Design and Supply ASIC Contract with European Industrial Customer

Oxford, UK

EnSilica, a leading chip maker of mixed signal ASICs (“Application Specific Integrated Circuits”), is pleased to announce that it has been awarded an $18m design and supply contract by a leading European based supplier of electromechanical products for a Cortex M series Arm-based mixed signal sensor interface ASIC to be used across a range of automotive and industrial applications. The total value of the contract is estimated to exceed $18m over seven years.

 

EnSilica has been selected due to its significant experience in developing mixed signal design ASICs, alongside a proven track record of bringing automotive and industrial chips to high volume production.

The part will be qualified to the stringent automotive standard AEC-Q100 grade 0 and EnSilica’s in-house functional safety flow will be used to design the ASIC to meet the requirements defined in ISO26262 Automotive Safety Integrity Level B (ASIL-B).

 

Ian Lankshear, CEO of EnSilica, commented: “This is another exciting design win that enhances our growing portfolio of ASICs and further improves the visibility of our recurring revenues from chip supply. This new European customer is highly respected in the industry and has a strong track record of shipping its products in high volume. This contract is a testament to the company’s ability to deliver high-quality, reliable solutions that meet the evolving needs of the market and further demonstrates our team’s commitment to excellence and innovation which continues to drive our success and position EnSilica as a premier European ASIC supplier.”