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EnSilica and Codasip announce strategic partnership

EnSilica and Codasip announce strategic partnership to bring CHERI cybersecurity to automotive, critical national infrastructure, defence and aerospace applications  

 

Oxfordshire, United Kingdom and Munich, Germany, – September 18, 2025: EnSilica, a fabless supplier of mixed-signal and digital ASICs, and Codasip, a provider of functionally-safe and cyber-resilient RISC-V CPUs, announces a strategic partnership to enable custom ASICs incorporating CHERI (Capability Hardware Enhanced RISC Instructions), Post-Quantum Cryptographic (PQC) acceleration, and advanced system-level security and safety features. These will serve industrial, automotive, critical national infrastructure, including defence and aerospace applications.

 

CHERI represents a transformative hardware security architecture designed to mitigate memory safety vulnerabilities, one of the most significant sources of modern cyberattacks, and provides fine-grained compartmentalisation to increase software robustness and resilience.

 

EnSilica will use Codasip’s portfolio of 32-bit and 64-bit CHERI RISC-V processors as the foundation for developing customer-specific System-on-Chip (SoC) integrated circuits. These secure platforms will integrate processing, PQC and classical encryption hardware, and tailored analogue and digital functionality to meet the precise requirements of the end application.

 

Ian Lankshear, CEO of EnSilica said: “Cybersecurity has become a defining challenge for automotive, industrial and defence systems, with attacks growing in scale and sophistication. This partnership positions EnSilica at the forefront of delivering cyber-resilient chips that combine CHERI’s hardware-enforced memory safety with post-quantum cryptography. By building on Codasip’s advanced CHERI RISC-V processors, we can offer customers complete, application-specific ASIC solutions with security and functional safety designed in from the ground up. We are excited to work with Codasip to bring this next generation of trusted silicon to market.”

 

Dr Ron Black, CEO of Codasip added: “The partnership will help to unlock the full potential or our leading-edge 32-bit and 64-bit CHERI RISC-V CPUs. Developed in line with ISO 26262 functional safety and ISO 21434 cybersecurity standards, our processors come with a complete ecosystem including CHERI toolchain, CHERI Linux, and CHERI RTOSes. By combining these with EnSilica’s ASIC expertise, we can accelerate the adoption of CHERI-based security in mission-critical applications.”

EnSilica Establishes New EU Mixed-Signal Design Centre in Budapest, Hungary

EnSilica is establishing of a new design centre in Budapest, Hungary.

 

The facility strengthens EnSilica’s presence in the European Union and taps into Budapest’s deep technology ecosystem, which hosts numerous leading automotive and industrial multinationals. This expansion will increase the Group’s global headcount to around 210 employees.

 

By the end of September 2025, the Budapest team will comprise 16 experienced engineers, many with 10 to 20 years’ expertise in mixed-signal chip design. Their technical excellence and collaborative approach are closely aligned with EnSilica’s culture and growth strategy.

 

The centre will focus on developing advanced mixed-signal designs for industrial and automotive applications, providing additional EU-based design capacity to support recent design wins and a strong pipeline of opportunities.

 

EnSilica’s operations now span four UK engineering design centres in Abingdon, Sheffield, Bristol, and Cambridge, alongside international facilities in Bangalore (India), Porto Alegre and Campinas (Brazil), and Budapest (Hungary).

 

Ian Lankshear, Chief Executive Officer of EnSilica, commented: “We are delighted to establish a base in Budapest, a city which has rapidly become a key technology hub in the EU. EnSilica continues to attract exceptionally talented engineers at a time when there is a significant global talent shortage, and this strategic move will allow us to further strengthen our position in our focused market segments to ensure we are ideally placed to capitalise on exciting near-term growth opportunities.”

EnSilica cuts post-quantum cryptography (PQC) silicon area with three-in-one IP block

Oxford, UK, July 21, 2025: EnSilica, a leading maker of mixed-signal ASICs (Application Specific Integrated Circuits), has developed a combined hardware IP block supporting the full CRYSTALS post-quantum cryptography (PQC) suite, saving silicon area, power and cost. The licensable eSi-CRYSTALS PQC accelerator runs Dilithium (FIPS-204), Kyber (FIPS-203) and SHA-3 (FIPS-202) algorithms, which previously required three separate IP blocks.

 

In August 2024, the US National Institute of Standards and Technology (NIST) released the first three finalised PQC standards, with additional algorithms announced or in draft stages. Dilithium, Kyber, and SHA-3 are advanced cryptographic algorithms designed to secure digital systems against both classical and quantum computing threats. Dilithium is used for digital signatures, providing authentication and data integrity, while Kyber is a key encapsulation mechanism that enables secure key exchange. Integrated into the block is also a hardware-optimised implementation of the cryptographic SHA-3 hash function that creates a digital fingerprint of data allowing for robust integrity verification. Together, these algorithms form the foundation for quantum-resistant security in modern systems, ensuring long-term protection of sensitive information.

 

Ian Lankshear, CEO of EnSilica, commented: “The emerging PQC threat is not just theoretical. Security analysts warn that adversaries can already capture encrypted data today, with the intention of decrypting it in the future when quantum capabilities become available, a tactic known as ‘harvest now, decrypt later’. The implications are profound for those relying on today’s cryptographic schemes, which is why EnSilica’s PQC offering delivers future-proof hardware protection at the silicon level with minimal silicon area for mature and advanced technology nodes.”

 

EnSilica previously announced separate Dilithium, Kyber and SHA-3 algorithms licensed for use by a major semiconductor company for a 5 nm networking ASIC. The new IP offers a more compact implementation than separate cores. EnSilica also has a full suite of classical cryptographic accelerators including ECC, ECDSA, RSA, AES, ChaCha20, and Poly1305. In addition, the company offers a NIST-compliant true random number generator (TRNG).

 

EnSilica Presents Innovation in Silicon-Based Satellite Communications at ISCAS 2025

EnSilica was proud to take part in the IEEE ISCAS 2025 conference, held in London this May, where Omotade Iluromi presented during the Industry Innovation Track.

His talk, titled “Closing the Communications Link to Space with Silicon Systems,” explored how modern silicon technologies are enabling transformative advances in satellite communications. The presentation focused on the role of silicon circuits and systems in meeting the challenges of broadband connectivity — from NGSO constellations and ground terminals to direct-to-handset applications.

Omotade also highlighted EnSilica’s ongoing development of low-cost, high-performance satellite communications ASICs, including Ku and Ka-band RFICs and digital beamformer ICs for both ground and satellite applications.

We’re excited to continue pushing the boundaries of what’s possible in space-based communications.

EnSilica establishes new engineering hub in Cambridge, UK

EnSilica, a leading maker of mixed-signal ASICs (Application Specific Integrated Circuits), has announced it has established a new engineering hub in Cambridge, UK.

 

Drawing on Cambridge’s renowned semiconductor ecosystem, EnSilica has opened a new engineering facility in the city and has recruited six engineers, four of whom hold PhDs, increasing the company’s global workforce to 190.

 

With the addition of this new facility and technical expertise, EnSilica will expand its existing mmWave / RF integrated circuit design capabilities, an area in which the company has already seen significant customer demand. The expansion has been facilitated by the recent UK Space Agency C-LEO-funded award, alongside additional contract momentum and customer wins that continue to support the company’s growth.

 

EnSilica currently operates across three UK engineering design centres in Abingdon, Sheffield and Bristol, alongside additional international engineering facilities in Bangalore, India, and Porto Alegre and Campinas in Brazil.

 

Ian Lankshear, Chief Executive Officer of EnSilica, commented: “We are delighted to have not only secured a team of highly skilled engineers at a time when there is a very real shortage of engineering talent in the UK, but also to establish a firm base in an established UK tech hub like Cambridge, which ideally positions the business to attract additional talent. By further expanding our engineering know-how across the satellite and communications market, I believe that this investment will enable the business to capitalise further on very real and near-term growth opportunities.”

 

EnSilica expands satcoms user terminal portfolio with dual-beam, dual-polarization Ku-band analogue beamformer chipset

Oxford, UK, : EnSilica, a leading maker of mixed-signal ASICs, has announced two Ku-band beamformer integrated circuits, the ENS92051 and ENS92052, which offer best-in-class power consumption and performance. They are designed to address the needs of the next generation of electronically steered antennas for a range of user terminals used with LEO, MEO and GEO satellite constellations.

 

The ENS92051 is the dual-beam Ku-band receiver (Rx) supporting eight channels with separate amplitude and phase control. The Rx carrier frequency range is 10.7 to 12.75 GHz.

 

The ENS92052 is the Ku-band transmitter supporting eight channels with separate amplitude and phase control. The Tx carrier frequency range 13.75 to 14.5 GHz.

 

The eight channels of the chipset can support four dual-polarisation or eight single-polarisation elements.  The highly integrated devices offer low-power and low-cost using phase and amplitude controls with a built-in temperature sensor, and the transmitter has an integral power detector.  The chipset includes a beam table to support very low-latency beam switching and supports a range of power-saving modes.

 

The device SPI bus and control pins operate from standard 1.8V logic at speeds up to 50 MHz, the core voltage is 1.0 V.  Both chips come in a 63-pin Wafer Level Chip Scale Package.

 

The devices will be fabricated and tested in Europe, offering customers a European sovereign supply chain. They are designed to meet the requirements of DO-254 DAL 5 and qualified to AEC-Q100 automotive grade 2.

 

Paul Morris, VP of RF & Communication BU commented:

 

“The addition of these Ku-band beamformer ICs to our portfolio enables our customers to develop the lowest power user terminals which can connect to existing constellations such as Eutelsat/OneWeb.  They also boost the European supply chain in satellite communications which has become increasingly important in recent months.”

 

The chipset is available for sampling to lead customers.

 

EnSilica Agrees $18m Design and Supply ASIC Contract with European Industrial Customer

Oxford, UK

EnSilica, a leading chip maker of mixed signal ASICs (“Application Specific Integrated Circuits”), is pleased to announce that it has been awarded an $18m design and supply contract by a leading European based supplier of electromechanical products for a Cortex M series Arm-based mixed signal sensor interface ASIC to be used across a range of automotive and industrial applications. The total value of the contract is estimated to exceed $18m over seven years.

 

EnSilica has been selected due to its significant experience in developing mixed signal design ASICs, alongside a proven track record of bringing automotive and industrial chips to high volume production.

The part will be qualified to the stringent automotive standard AEC-Q100 grade 0 and EnSilica’s in-house functional safety flow will be used to design the ASIC to meet the requirements defined in ISO26262 Automotive Safety Integrity Level B (ASIL-B).

 

Ian Lankshear, CEO of EnSilica, commented: “This is another exciting design win that enhances our growing portfolio of ASICs and further improves the visibility of our recurring revenues from chip supply. This new European customer is highly respected in the industry and has a strong track record of shipping its products in high volume. This contract is a testament to the company’s ability to deliver high-quality, reliable solutions that meet the evolving needs of the market and further demonstrates our team’s commitment to excellence and innovation which continues to drive our success and position EnSilica as a premier European ASIC supplier.”

EnSilica Opens Second Brazilian Design Centre Following Multimillion Pound Design and Manufacturing Contract Win

 

Oxford, UK

EnSilica, a leading maker of mixed-signal ASICs, has opened a second design centre in Brazil after a series of design wins, the most recent being a multimillion-pound design and manufacturing contract from an optical computing systems customer. The new design centre is in Campinas, São Paulo State, and complements the company’s Porto Alegre facility in Rio Grande do Sul, in southeastern Brazil.

 

 

Through strengthened relationships with key wafer foundry and semiconductor supply chain partners. EnSilica increasingly provides not only design services but also wafers, packages, and tested devices. This model, which has been successfully developed by several leading Asian chip design companies, is now being leveraged by EnSilica to meet the growing demand for a resilient European-based supply chain.

 

Campinas was chosen for its strong semiconductor ecosystem, which has enabled rapid growth of EnSilica’s existing engineering team in the region.

 

EnSilica CEO, Ian Lankshear, commented: “We are pleased to secure this sizable contract with a pioneering optical computing systems company. This agreement not only underscores our capabilities in delivering comprehensive design and manufacturing services but also highlights the growing demand for European-based supply chains. Our strengthened relationships with key wafer foundry and semiconductor supply chain partners enable us to provide high-quality wafers, packages, and completed tested devices. We are also delighted to be opening our second design centre in Brazil, which further underscores our strategic ambitions to expand our global footprint in order to meet the increasing demand for our services.”

European Space Agency and EnSilica partner to enable fully integrated ASICs for resilient GNSS

In partnership with the European Space Agency (ESA), EnSilica, a leading maker of mixed-signal ASICs, will design and develop a key silicon component to enable next-generation resilient multi-band Global Navigation Satellite System (“GNSS”) capabilities. These are vital to ensuring the world’s critical infrastructure and services remain robust and secure in the face of evolving global threats.

 

EnSilica will design and develop a key silicon component to enable next-generation resilient multi-band Global Navigation Satellite System (“GNSS”) capabilities, which are vital to ensuring the world’s critical infrastructure and services remain robust and secure in the face of evolving global threats.

 

The ESA, NAVISP Element 2 programme helps to increase the competitiveness of participating European states in the global market for satellite navigation and enables these countries to be well positioned to capitalise on emerging market opportunities across Positioning, Navigation and Timing (“PNT”) technologies and services.

 

EnSilica has a growing satellite communications market footprint and is working with support from ESA and UKSA, with the latter organisation awarding the Company £10.38 million in February 2025 for a development project under its Connectivity in Low Earth Orbit programme. Part of the company’s expertise is in architecting and implementing systems-on-chip with high-performance RF, including mmWave, and complex baseband processing.

 

Paul Morris, VP RF and Communications Business Unit at EnSilica, said, “As we and our infrastructure become ever more dependent on PNT services in everyday life, it is important to have highly integrated, resilient, and precise technology sourced in Europe and the UK. This collaboration will allow us to accelerate such technology, starting with a next-generation radio design enabling our partners to focus on integrating their custom algorithms.”

 

Ian Lankshear, Chief Executive Officer of EnSilica, added, “I am extremely proud of our team to have been secured this agreement under the ESA NAVISP Element 2. This project will enable us to further enhance global navigation satellite systems technology and continue to develop commercial solutions that are critical for resilient and reliable satellite navigation. We are grateful for the ongoing support from ESA and the UKSA, and we continue to focus on PNT and the broader satellite communications market as a key growth driver of our business.”