FPGA Design

Good quality HDL code ensures good quality of results from synthesis and facilitates efficient reuse. EnSilica has extensive experience in creating a broad range of designs using both VHDL and Verilog, based upon a robust set of coding guidelines.

Some FPGA designers take the ‘blow and go’ approach to verifying and debugging their design, This may work for smaller CPLDs and FPGAs but the odds of creating a multimillion-gate design and then debugging it successfully on the bench in a reasonable amount of time are very small.

EnSilica employs software-based simulation of FPGA design in much the same way as our ASIC development team has been applying for years. For pre-verified IP there needs to be a pragmatic approach to minimize the verification effort but a simulation environment should be available to allow reported system issues to be re-created in a software-based simulation. This approach minimizes the time spent debugging on the bench and allows corner case verification cases to be developed and functional coverage to be measured. Our methodology has been proven over the many years we have been developing products for our customers to reduce the overall time-to-market and improve the reliability of the products in the field.

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EnSilica will utilize the FPGA vendors growing array of high-quality, technology optimized IP as required to make sure that the overall requirements are met with the minimum of new design and verification effort. In some cases specialist third party IP may need to be procured. EnSilica understand the technical and commercial issues in selecting and integrating IP cores. Our own IP library can be drawn upon to accelerate the project development. The library components are FPGA vendor independent, allowing the designs to be migrated between FPGA vendors or even re-targeted to an ASIC. Some of our IP cores have been designed to overcome identified short coming in a specific FPGA vendor IP cores. EnSilica’s growing IP portfolio provides a broad set of Communication, DSP and Radar algorithm acceleration.

There was a time that just setting a global maximum clock frequency would constrain an FPGA design. Modern FPGA devices support multi-clock domains, multiple PLLs and high-speed interfaces such as DDR3. FPGA tools have matured offer the past few years, and now include accurate static timing engines supporting ASIC compatible constraint scripting languages.

For reliable operations across all process, temperature and voltage corners, timing constraints need to be developed and static timing carried out after each fitting to ensure that the design will work in the intended environment. EnSilica apply their expertise developed on high-complexity ASIC designs to generate real world timing constraints and achieve the required timing in the optimum speed grade device.

Moving to the next fastest speed grade in your chosen FPGA can increase your unit component price by 20 to 30%. Even the IP supplied by the specific FPGA vendor might not be optimised to make the most efficient use of the available resources on the device, resulting in a move to the next largest device increasing the product cost significantly.

In many cases unit cost is secondary to time-to-market and getting the design to the customer is the overriding requirement. When unit cost becomes important EnSilica’s expert FPGA designers can take either a top-down approach to reduce the cost of the FPGA device or use advance fitting and floor planning to fit the device in a slower speed-grade or smaller part, or even migrate the design to a low-cost family of devices.