Managing tradeoffs in ASIC design for low-power, small-form-factor wearable medical devices



Here EnSilica’s Konstantinos Glaros examines some key tradeoffs OEMs will likely face 

when taking an ASIC approach and how to balance these tradeoffs more effectively.

Wearable technology for healthcare and wellness applications represents a tremendous opportunity. The potential designs range from smart plasters through wrist monitors to therapeutic systems. But a common set of constraints unites many of these devices, the most important of which are accuracy, energy usage, size and cost. Though each of these has an important bearing on the hardware design, the tradeoffs that designers need to face will often focus primarily on the device’s energy profile. How power consumption changes with activity frequently dominates architectural decisions and the degree to which design can satisfy the other constraints.


Tradeoff 1: Always on vs battery sizesmart watch image

The capacity of an attached battery will restrict the energy that can be supplied to the device. Battery-less designs that employ energy harvesting will be even more constrained. The energy limitation will control several aspects of the design. From a system-design standpoint, the decision with the greatest impact at all levels is that of the duty cycle.


Though many healthcare devices present themselves as “always on”, for much of the time an efficient design will ensure most of the circuitry will run on a low duty cycle: asleep and powered down for as long as possible before being called into action. In modern process nodes, power gating is essential, to prevent the constantly flowing leakage current in powered transistors. Implementing multiple clock and power domains, for example, ensures power is supplied only to the subsystems that need it at the right time.


Many times, the only part of the system that is active at all times is a highly power-efficient timer and memory buffer that periodically wakes the front-end circuitry to perform a data conversion and move the data into the buffer. Circuitry or firmware may monitor the incoming data to see if certain thresholds have been exceeded or if the buffer is full. If so, the logic can trigger a state transition that wakes up a supervisory microcontroller to analyze the data. Decisions made at that level may lead to more parts of the system being woken up to take further action. That action may take the form of relaying data to another IoT device or smartphone host over Bluetooth.


Though the sleep and wake cycles can be managed at the software or firmware level, this is not necessarily optimal for power efficiency. This is one reason using a front-end ASIC can deliver a significant advantage when full-system power consumption is considered. A front-end ASIC can often provide the ability to fine-tune control of power states that may not be available in the predefined states of an off-the-shelf front-end data converter.


Tradeoff 2: Performance vs battery size


Many off-the-shelf high-resolution ADCs employ a sigma-delta architecture. icon imageIn this architecture, a digital filter section trades sample rate for resolution from a relatively simple analog input stage, a design approach that provides high accuracy and dynamic range at relatively low cost in modern semiconductor processes. The high dynamic range can help manage interference in healthcare devices, where there is often significant noise mixed in with the signal of interest.


Digital signal processing of the captures by a relatively powerful processor can filter out much of the noise and interferers from what may be a relatively small signal of interest. Unfortunately, this combination of strategies leads to a power-hungry system. Significant energy is not just required for the oversampling and filtering performed by the DSP, but also in the extensive digital post-processing needed on the host microcontroller, which may need to be active for each capture. This issue can be exacerbated by the high latency of sigma-delta converters when decimation filters are scaled up to achieve high resolution. The time required to obtain each block of samples from the start of the capture sequence can lead to an increase in the duty-cycle ratio of the host microcontroller/system.

A more energy-efficient solution is to focus on handling interference closer to the source and use mixed-signal circuitry to deal with common noise sources so that a cleaner, lower-rate signal can be relayed to the host microcontroller. This type of design often employs custom DSP on the ASIC to carry out the digital filtering of the oversampled signal for two purposes. By removing the effects of large interferers at the source, it is possible to reduce the dynamic range requirement for the ADC. Second, the filtered signal can be transmitted to the microprocessor using a lower sample rate, which reduces circuit activity and, consequently, power. Further savings can be made by buffering some output samples in memory on the ASIC, waking the microcontroller at infrequent intervals to read them out and process them. At the limit, only specific signal features or events, such as an abnormal heart-rate value, may be transmitted, to be logged, or wake up the system for further action. As the output sample rate is now low, further power savings can also be gained by storing the output samples in memory on the ASIC and only waking up the microcontroller very infrequently to read them out.


With less need for high dynamic range, the resulting ASIC can, in turn, employ a far less energy-intensive conversion architecture. It may still be a sigma-delta converter, but one that employs a simpler, lower-latency decimation filter stage. Such a design has a shorter startup overhead which lends itself to faster power-up and power-down cycles or multiplexing across input channels. Another option is a successive-approximation (SAR) design, as this is an architecture that delivers high energy efficiency overall. For slowly changing inputs, a charge-integrating circuit may offer the best combination of energy usage, resolution, and capture rate.


Tradeoff 3: Functionality vs form factor?

An important characteristic of front-end ASICs is that they can be very space efficient. It is common for the silicon to measure less than 3 x 3mm, making the devices highly suitable for the small package sizes of healthcare wearables. However, the use of chip-scale packages that take full advantage of the ASIC’s compact nature will cause a limited number of I/O connections from the device. This works in opposition to the trend of building more sensor inputs into the system. Multiple inputs provide the ability to probe more skin sites in order to obtain a better signal. Smart healthcare wearables are increasingly combining data from different sensor modalities to improve overall results and, at the same time, deal more effectively with noise from individual inputs.


A conventional method to balance the tradeoff between chip size and an increase in I/O connections is to move to packages that offer a higher pitch density than the standard pitch of 0.4mm. The trade-off is that this will probably increase overall system cost because of changes that will be needed in the PCB and assembly technology to handle the finer-pitch circuit traces. Another option is to increase the level of multiplexing on I/O channels, particularly for connections to an external microcontroller.


Multiplexing over serial ports provides an efficient way of trading pin count against data throughput. There is flexibility in terms of which protocol to use. If it can support the device’s required data rate, using two-wire I2C rather than four-wire SPI frees up two potentially precious I/O pins.


A further source of saving in terms of pin count is through circuit design techniques that avoid the need to use external passives, such as capacitors and inductors, to handle analog-processing functions. Mixed-signal processes offered by foundries allow passive elements to be formed in the metal interconnect stack and can provide an effective trade off of die size against pin count.


It’s also worth mentioning that advanced packaging techniques will also free up PCB real estate and IO pins by embedding both the analog front end and sensors in a single package.

Tradeoff 4: Reduced BoM vs cost?

In an ideal world, most of the functions of a system would be absorbed into a single ASIC. But there are several cases where this would not be economically viable.


What functions are integrated into an ASIC and the process node the ASIC will need to implement them will be affected by a huge number of requirements. They include voltage levels, IP availability, support for nonvolatile memory, the number of logic gates required, and cost. Analog interfaces and other support circuitry will often show better economics on mature process nodes with transistors and other integrated components not scaling as logic or memory transistors do.


You may not be able to have everything you want, but a good ASIC designer will be able to balance tradeoffs and look at the complete system to find you the best option.


A good example of the tradeoffs at work is a glucose monitoring patch. This type of device needs an analog front-end, BLE support for wireless communications, a processor core and flash memory. Assuming a 55nm target process, the total ASIC development cost could reach several million US dollars. This would not just be for the design and creation of the masks used for production at the fab, but licensing the BLE and processor IP.


A more cost-effective way of approaching the same design would be to use an analog front-end ASIC that is designed to work with a variety of off-the-shelf BLE-enabled processors. The flexibility to support different external processors would allow manufacturing changes if supply-chain conditions demand it.


Doing so would demand duplication of some functions in the ASIC, possibly requiring additional general-purpose I/O and I2C or SPI interfaces, together with power-management interfaces. This may add to the ASIC’s size and therefore cost. But bigger savings could be achieved. The ASIC would be able to use a mature process with lower mask costs, such as 130nm. And the ASIC would require less IP to be licensed, which will reduce the development cost. But the architecture would still deliver supply-chain protection.



Taking an ASIC approach gives protection from supply chain issues and allows you to optimize your design. But there are always tradeoffs, and these should be understood before taking this route.

Medical ASICs: Balancing Power and Performance in Wearable Technologies

When it comes to medical devices, navigating the intricate world of ASICs is something of a tightrope walk. Each step of the design phase involves striking a delicate balance between power, efficiency, and performance, where every gain comes at a cost. Medical ASICs are the beating hearts of potentially life-saving devices that must remain operational around the clock, yet are constrained by the finite capacity of their batteries. In this first part of our two-part blog series, we explore the nuanced tradeoffs that define ASIC design in medical applications, focusing on the harmonization of “always-on” functionality with the critical limitations of power resources, and how these factors interplay to shape battery size and device performance.

Balancing “always on” demands with battery capabilities

The need for “always on” functionality is now commonplace, but nowhere is it more crucial than in the development of wearable medical devices. This presents a formidable challenge when it comes to designing medical ASICs, where high performance meets the stark reality of limited battery capabilities. That’s why custom ASICs, the linchpins in these medical devices, are increasingly engineered with a keen focus on striking this critical balance. But it’s not easy. The battery’s capacity, a finite resource, automatically becomes the defining factor for the device’s energy management and overall functionality. This limitation is even more acute in devices that eschew traditional batteries for innovative energy-harvesting solutions.


However, there are ways of managing this trade-off, particularly when it comes to the strategic decision-making around the device’s duty cycle. Despite the “always on” label, an optimally designed medical device actually spends much of its time in a low-power state, conserving energy by remaining dormant until needed. This is where the ingenuity of custom ASICs shines, employing power gating as an essential tool to control leakage current in transistors – a persistent issue in medical ASICs.


The solution often lies in creating multiple clock and power domains within the ASIC, allowing power to be judiciously supplied to specific subsystems only when necessary. Typically, the most consistently active elements are a low-power timer and a memory buffer, which periodically activate the front-end circuitry for brief data conversion and storage tasks. This selective engagement, a hallmark of sophisticated ASIC design, is pivotal in marrying the necessity of “always-on” functionality with the stringent power limitations that are a hallmark of modern medical devices.


Optimizing performance with limited battery size

The pursuit of high performance in medical ASICs often leads designers into something of a struggle with battery size. High-resolution Analog-to-Digital Converters (ADCs), a staple in many medical devices for their accuracy and dynamic range, typically employ a sigma-delta architecture. This architecture, while cost-effective and precise, can be a significant drain on power resources. The challenge here is to achieve the necessary performance without imposing undue demands on the battery.


In sigma-delta ADCs, a digital filter section effectively trades sample rate for resolution, derived from a relatively simple analog input stage. This setup is ideal for managing interference in noisy environments, common in medical applications. However, the downside is the substantial energy required not just for the oversampling and filtering by the Digital Signal Processor (DSP), but also for the extensive digital post-processing on the host microcontroller. Each capture cycle, therefore, becomes a power-intensive operation, exacerbated by the high latency characteristic of sigma-delta converters, especially when high resolution is desired.


A more energy-efficient approach involves tackling interference closer to its source, using mixed-signal circuitry within the ASIC to address common noise sources. This strategy allows for a cleaner, lower-rate signal to be sent to the microcontroller, reducing overall circuit activity and, consequently, power consumption. Custom DSPs integrated into the ASIC can perform digital filtering of the oversampled signal, achieving two critical goals: reducing the dynamic range requirement for the ADC and enabling transmission of the filtered signal at a lower sample rate. This not only conserves power but also allows for the buffering of output samples within the ASIC, reducing the frequency at which the microcontroller needs to wake up for data processing. In some designs, only specific signal features or events, such as abnormal heart-rate readings, are transmitted, further minimizing power usage and maximizing the efficiency of medical ASICs.


Final thoughts

When it comes to designing medical ASICs, the tradeoffs between “always-on” functionality, performance, and battery size are not just challenges; they’re also opportunities for innovation and optimization. As we have explored, the key lies in intelligent design choices that balance these competing demands, ensuring that medical devices deliver on their promise of reliability and efficiency. Custom ASICs, with their ability to finely tune power states and manage energy consumption smartly, are the counterweights key to mastering this balancing act.


However, the exploration of power and performance tradeoffs is just the beginning. In the next article in this two-part series, we’ll delve into the equally critical aspects of functionality versus form factor and the balancing act between reducing the Bill of Materials (BoM) and managing costs. These considerations are pivotal in shaping the final design and effectiveness of medical ASICs, further demonstrating the nuanced complexity of ASIC design in the medical field. Remember, in this high-stakes arena, understanding and managing these tradeoffs is not just about technical proficiency; it’s about crafting solutions that ultimately enhance patient care and safety.


For more information, contact EnSilica’s expert team

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How to write an ASIC design specification well – Part 3

This is a 3 part blog. If you missed it, click here to read part 1 and part 2.

The 7 Most Common Mistakes and How To Avoid Them

The first step in developing a new ASIC for any function – be it a wireless chip for a wearable healthcare sensor device, an autonomous vehicle ASIC, or a communications system for a satellite – is the specification.

To ensure the product you need is produced, is done so on time and on budget, and that errors aren’t introduced that could require a recall, the specification has to be written clearly and concisely.

In this, the final part, we look at the most common mistakes and how to avoid them.

1) Loose language

The language used in the document matters. It can add clarity, and it can add ambiguity.
For example, there is a big difference between ‘shall’ (expresses a requirement), ‘will’ (makes a statement of fact), and ‘should’ (expresses an aspiration).

2) Not being concise

Requirements should be as concise as possible, and broken down into individual items to give full clarity when reporting compliance during the development.
For example, it is better to say, “The product must do X” and “The product should do Y” versus “The product must do X and should do Y”.

3) Missing information

Any aspect of the product’s functionality that is missing from the requirements will not make it to specification document. And, therefore, will be missing in the product.

4) Lacking rationales

Rationales should be added for each requirement where appropriate.
But note, these should not be extensions of the requirement. And compliance will be determined against the requirement, not the rationale.

5) How vs what

The requirements describe what the product must do rather than how it must provide that functionality.

6) Including non-essential functionality

If something is not essential for the intended product functionality, then it should not be a requirement.

7) Lacking measurability

Requirements should be clear and unambiguous, and terminologies or expressions that are not verifiable should be avoided all costs.

This means subjective statements like “The product must be low power” should be defined to say “The product must consume less than X”.

And for reporting compliance, there must be a way to uniquely identify each requirement. This enables compliance reports to make clear statements such as “Specification S.17 addresses requirement R.49”.

Getting a specification wrong can be catastrophic. By following these seven tips you’ll be well-placed to get it right first time.

If you want to find out more about how EnSilica can help, click here.

How to write an ASIC design specification well – Part 2

This is a 3 part blog. If you missed it, click here to read part 1.

Who Is The Specification For

The first step in developing a new ASIC for any function – be it a wireless chip for a wearable healthcare sensor device, an autonomous vehicle ASIC, or a communications system for a satellite – is the specification.

To ensure the product you need is produced, is done so on time and on budget, and that errors aren’t introduced that could require a recall, the specification has to be written clearly and concisely.
In this, the second of three blogs on the topic, we look at the audiences for needs the specification and the information they need.

“The specification can (and does) act as the communication channel, helping information to flow.”

Who reads it?

There are two audiences.

1) Your internal system development team. If they lack understanding or agreement of the product’s definition, there’s little chance that the development team can successfully deliver what is required.

2) Our development team. Because it’s natural and common for individual members in a development team to read the sections of the specification focused on their tasks… and only these sections, the specification document allows a development team to be structured correctly and the right skill sets brought together to get it right first time.

Potential pitfalls

However, the specification document does not act as a panacea to magically resolve poor communication between customer and supplier. Nor will it fix potential communication problems between people within a development team, however it can (and does) act as the communication channel, helping information to flow.

If you want to find out more about how EnSilica can help, click here.

Click here to read part 1 and part 3.

How to write an ASIC design specification well – Part 1

The Purpose Of The Specification

The first step in developing a new ASIC for any function – be it a wireless chip for a wearable healthcare sensor device, an autonomous vehicle ASIC, or a communications system for a satellite – is the specification.

To ensure the product you need is produced, is done so on time and on budget, and that errors aren’t introduced that could require a recall, the specification has to be written clearly and concisely.
In this, the first of three blogs on the topic, we look at the purpose of the specification to help you avoid some of the most common mistakes.

“One common misconception is that the specification can serve as a datasheet or user manual. It cannot and does not.”

The specification’s purpose

To get it designs right first time, it is crucial to clearly define the required functionality and behaviours that the product must possess; and the specification is there to define these. And to also state that any functionality that is explicitly not required.

Who writes it

Typically, the engineering team generates the specification in collaboration with the end customer. It will be based on a requirements document, which will be provided by the customer.

What the document enables

Instead, the primary role of a specification is to unambiguously set out the customer’s requirements. With each customer requirement directly or indirectly addressed by the functionality defined in the specification.

There should be a clear mapping, (one-to-one / one-to-many), between each customer requirement and each function defined in the specification.

What it should not be used for

One common misconception is that the specification can serve as a datasheet or user manual. It cannot and does not.

What happens once it’s written

Once written, it is essential for the customer and development team to thoroughly review and approve the specification and ensure it adequately meets each requirement.

Additionally, the compliance report prepared by the development team should be reviewed and approved by the customer to make sure everything has been interpreted correctly.

If you want to find out more about how EnSilica can help, click here.

Click here to read part 2 and part 3.